Fix comment

Signed-off-by: Mikhail R. Gadelha <[email protected]>

Author: mikhailramalho

llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td

@@ -70,8 +70,8 @@ def : WriteRes<WriteIMul32, [SMX60_IEU]>  { let Latency = 3; }
 def : WriteRes<WriteIMul, [SMX60_IEU]>  { let Latency = 6; }
 
 // Integer division/remainder
-// TODO: our experiments show that the latency of div is 4, which
-// seems too low. We used the worst case latency from the C908 instead.
+// TODO: Latency set based on C908 datasheet and hasn't been
+// confirmed experimentally.
 let Latency = 12, ReleaseAtCycles = [12] in {
   def : WriteRes<WriteIDiv32, [SMX60_IEUA]>;
   def : WriteRes<WriteIRem32, [SMX60_IEUA]>;