@@ -713,8 +713,8 @@ MachineInstrBuilder SIPreEmitPeephole::createUnpackedMI(MachineInstr &I,
713713 bool IsHiBits) {
714714 MachineBasicBlock &MBB = *I.getParent ();
715715 const DebugLoc &DL = I.getDebugLoc ();
716- const MachineOperand *SrcMO1 = TII->getNamedOperand (I, AMDGPU::OpName::src0);
717- const MachineOperand *SrcMO2 = TII->getNamedOperand (I, AMDGPU::OpName::src1);
716+ const MachineOperand *SrcMO0 = TII->getNamedOperand (I, AMDGPU::OpName::src0);
717+ const MachineOperand *SrcMO1 = TII->getNamedOperand (I, AMDGPU::OpName::src1);
718718 Register DstReg = I.getOperand (0 ).getReg ();
719719 unsigned OpCode = I.getOpcode ();
720720 Register UnpackedDstReg = IsHiBits ? TRI->getSubReg (DstReg, AMDGPU::sub1)
@@ -730,11 +730,12 @@ MachineInstrBuilder SIPreEmitPeephole::createUnpackedMI(MachineInstr &I,
730730 NewMI.addDef (UnpackedDstReg); // vdst
731731 if (AMDGPU::hasNamedOperand (UnpackedOpcode, AMDGPU::OpName::src0) &&
732732 AMDGPU::hasNamedOperand (UnpackedOpcode, AMDGPU::OpName::src1)) {
733- addOperandAndMods (NewMI, Src0Mods, IsHiBits, *SrcMO1 );
734- addOperandAndMods (NewMI, Src1Mods, IsHiBits, *SrcMO2 );
733+ addOperandAndMods (NewMI, Src0Mods, IsHiBits, *SrcMO0 );
734+ addOperandAndMods (NewMI, Src1Mods, IsHiBits, *SrcMO1 );
735735 } else {
736- const MachineOperand *SrcMO = IsHiBits ? SrcMO2 : SrcMO1;
737- addOperandAndMods (NewMI, Src1Mods, IsHiBits, *SrcMO);
736+ const MachineOperand *SrcMO = IsHiBits ? SrcMO1 : SrcMO0;
737+ unsigned SrcMods = IsHiBits ? Src1Mods : Src0Mods;
738+ addOperandAndMods (NewMI, SrcMods, IsHiBits, *SrcMO);
738739 }
739740
740741 if (AMDGPU::hasNamedOperand (OpCode, AMDGPU::OpName::src2)) {
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