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JanekvO
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ronlieb
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Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)
Reverts #154115 Co-authored-by: ronlieb <[email protected]>
1 parent fc438d3 commit a584bd9

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6 files changed

+59
-99
lines changed

6 files changed

+59
-99
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -5287,30 +5287,6 @@ SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
52875287
return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
52885288
}
52895289

5290-
bool AMDGPUTargetLowering::isInt64ImmLegal(SDNode *N, SelectionDAG &DAG) const {
5291-
if (!Subtarget->isGCN())
5292-
return false;
5293-
5294-
ConstantSDNode *SDConstant = dyn_cast<ConstantSDNode>(N);
5295-
ConstantFPSDNode *SDFPConstant = dyn_cast<ConstantFPSDNode>(N);
5296-
auto &ST = DAG.getSubtarget<GCNSubtarget>();
5297-
const auto *TII = ST.getInstrInfo();
5298-
5299-
if (!ST.hasMovB64() || (!SDConstant && !SDFPConstant))
5300-
return false;
5301-
5302-
if (ST.has64BitLiterals())
5303-
return true;
5304-
5305-
if (SDConstant) {
5306-
const APInt &APVal = SDConstant->getAPIntValue();
5307-
return isUInt<32>(APVal.getZExtValue()) || TII->isInlineConstant(APVal);
5308-
}
5309-
5310-
APInt Val = SDFPConstant->getValueAPF().bitcastToAPInt();
5311-
return isUInt<32>(Val.getZExtValue()) || TII->isInlineConstant(Val);
5312-
}
5313-
53145290
SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53155291
DAGCombinerInfo &DCI) const {
53165292
SelectionDAG &DAG = DCI.DAG;
@@ -5360,8 +5336,6 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53605336
SDValue Src = N->getOperand(0);
53615337
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
53625338
SDLoc SL(N);
5363-
if (isInt64ImmLegal(C, DAG))
5364-
break;
53655339
uint64_t CVal = C->getZExtValue();
53665340
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
53675341
DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
@@ -5372,8 +5346,6 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
53725346
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Src)) {
53735347
const APInt &Val = C->getValueAPF().bitcastToAPInt();
53745348
SDLoc SL(N);
5375-
if (isInt64ImmLegal(C, DAG))
5376-
break;
53775349
uint64_t CVal = Val.getZExtValue();
53785350
SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
53795351
DAG.getConstant(Lo_32(CVal), SL, MVT::i32),

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -103,9 +103,6 @@ class AMDGPUTargetLowering : public TargetLowering {
103103
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
104104

105105
protected:
106-
/// Check whether value Val can be supported by v_mov_b64, for the current
107-
/// target.
108-
bool isInt64ImmLegal(SDNode *Val, SelectionDAG &DAG) const;
109106
bool shouldCombineMemoryType(EVT VT) const;
110107
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
111108
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -15198,36 +15198,13 @@ SITargetLowering::performExtractVectorEltCombine(SDNode *N,
1519815198
return V;
1519915199
}
1520015200

15201-
// EXTRACT_VECTOR_ELT (v2i32 bitcast (i64/f64:k), Idx)
15202-
// =>
15203-
// i32:Lo(k) if Idx == 0, or
15204-
// i32:Hi(k) if Idx == 1
15205-
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
15206-
if (Vec.getOpcode() == ISD::BITCAST && VecVT == MVT::v2i32 && Idx) {
15207-
SDLoc SL(N);
15208-
SDValue PeekThrough = Vec.getOperand(0);
15209-
auto *KImm = dyn_cast<ConstantSDNode>(PeekThrough);
15210-
if (KImm && KImm->getValueType(0).getSizeInBits() == 64) {
15211-
uint64_t KImmValue = KImm->getZExtValue();
15212-
return DAG.getConstant(
15213-
(KImmValue >> (32 * Idx->getZExtValue())) & 0xffffffff, SL, MVT::i32);
15214-
}
15215-
auto *KFPImm = dyn_cast<ConstantFPSDNode>(PeekThrough);
15216-
if (KFPImm && KFPImm->getValueType(0).getSizeInBits() == 64) {
15217-
uint64_t KFPImmValue =
15218-
KFPImm->getValueAPF().bitcastToAPInt().getZExtValue();
15219-
return DAG.getConstant((KFPImmValue >> (32 * Idx->getZExtValue())) &
15220-
0xffffffff,
15221-
SL, MVT::i32);
15222-
}
15223-
}
15224-
1522515201
if (!DCI.isBeforeLegalize())
1522615202
return SDValue();
1522715203

1522815204
// Try to turn sub-dword accesses of vectors into accesses of the same 32-bit
1522915205
// elements. This exposes more load reduction opportunities by replacing
1523015206
// multiple small extract_vector_elements with a single 32-bit extract.
15207+
auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1));
1523115208
if (isa<MemSDNode>(Vec) && VecEltSize <= 16 && VecEltVT.isByteSized() &&
1523215209
VecSize > 32 && VecSize % 32 == 0 && Idx) {
1523315210
EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT);

‎llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll‎

Lines changed: 28 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -7,18 +7,21 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
77
; CHECK-NEXT: s_load_dword s0, s[4:5], 0x8
88
; CHECK-NEXT: s_load_dwordx2 s[10:11], s[4:5], 0x0
99
; CHECK-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x10
10-
; CHECK-NEXT: v_mov_b32_e32 v30, 0x9037ab78
11-
; CHECK-NEXT: v_mov_b32_e32 v31, 0x3e21eeb6
10+
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3e21eeb6
11+
; CHECK-NEXT: v_mov_b32_e32 v20, 0
1212
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
1313
; CHECK-NEXT: s_bitcmp1_b32 s0, 0
1414
; CHECK-NEXT: s_cselect_b64 s[16:17], -1, 0
1515
; CHECK-NEXT: s_xor_b64 s[18:19], s[16:17], -1
1616
; CHECK-NEXT: s_bitcmp1_b32 s0, 8
1717
; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0
1818
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[2:3]
19-
; CHECK-NEXT: s_xor_b64 s[20:21], s[2:3], -1
2019
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0
20+
; CHECK-NEXT: v_mov_b32_e32 v0, 0x9037ab78
21+
; CHECK-NEXT: v_accvgpr_write_b32 a3, v1
22+
; CHECK-NEXT: s_xor_b64 s[20:21], s[2:3], -1
2123
; CHECK-NEXT: s_and_b64 s[2:3], exec, s[2:3]
24+
; CHECK-NEXT: v_accvgpr_write_b32 a2, v0
2225
; CHECK-NEXT: v_mov_b32_e32 v2, 0xa17f65f6
2326
; CHECK-NEXT: v_mov_b32_e32 v3, 0xbe927e4f
2427
; CHECK-NEXT: v_mov_b32_e32 v4, 0x19f4ec90
@@ -34,15 +37,14 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
3437
; CHECK-NEXT: v_mov_b32_e32 v14, 0x8427b883
3538
; CHECK-NEXT: v_mov_b32_e32 v15, 0x3fae1bb4
3639
; CHECK-NEXT: s_mov_b64 s[22:23], 0
37-
; CHECK-NEXT: v_mov_b32_e32 v20, 0x57b87036
38-
; CHECK-NEXT: v_mov_b32_e32 v21, 0x3fb3b136
40+
; CHECK-NEXT: v_mov_b32_e32 v0, 0x57b87036
41+
; CHECK-NEXT: v_mov_b32_e32 v1, 0x3fb3b136
3942
; CHECK-NEXT: s_and_b64 s[4:5], exec, s[16:17]
4043
; CHECK-NEXT: v_mov_b32_e32 v18, 0x55555523
4144
; CHECK-NEXT: v_mov_b32_e32 v19, 0xbfd55555
4245
; CHECK-NEXT: s_and_b64 s[6:7], exec, s[18:19]
43-
; CHECK-NEXT: v_mov_b32_e32 v0, 0
44-
; CHECK-NEXT: v_mov_b64_e32 v[16:17], 0
45-
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
46+
; CHECK-NEXT: v_mov_b32_e32 v21, v20
47+
; CHECK-NEXT: ; implicit-def: $vgpr30_vgpr31
4648
; CHECK-NEXT: ; implicit-def: $vgpr22_vgpr23
4749
; CHECK-NEXT: s_branch .LBB0_2
4850
; CHECK-NEXT: .LBB0_1: ; %Flow9
@@ -62,11 +64,12 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
6264
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
6365
; CHECK-NEXT: v_mov_b64_e32 v[24:25], s[14:15]
6466
; CHECK-NEXT: flat_load_dwordx2 v[24:25], v[24:25]
65-
; CHECK-NEXT: v_mov_b64_e32 v[26:27], v[30:31]
67+
; CHECK-NEXT: v_accvgpr_read_b32 v27, a3
68+
; CHECK-NEXT: v_accvgpr_read_b32 v26, a2
6669
; CHECK-NEXT: v_mov_b64_e32 v[28:29], v[2:3]
67-
; CHECK-NEXT: v_mov_b64_e32 v[16:17], v[20:21]
68-
; CHECK-NEXT: v_accvgpr_write_b32 a2, 0
69-
; CHECK-NEXT: v_accvgpr_write_b32 a3, 0
70+
; CHECK-NEXT: v_mov_b64_e32 v[16:17], v[0:1]
71+
; CHECK-NEXT: v_accvgpr_write_b32 a0, 0
72+
; CHECK-NEXT: v_accvgpr_write_b32 a1, 0
7073
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
7174
; CHECK-NEXT: v_fmac_f64_e32 v[26:27], 0, v[24:25]
7275
; CHECK-NEXT: v_fmac_f64_e32 v[28:29], 0, v[26:27]
@@ -93,32 +96,30 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
9396
; CHECK-NEXT: .LBB0_6: ; %.preheader1855.i.i.i3329
9497
; CHECK-NEXT: ; Parent Loop BB0_2 Depth=1
9598
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
96-
; CHECK-NEXT: v_accvgpr_read_b32 v29, a3
97-
; CHECK-NEXT: v_accvgpr_read_b32 v28, a2
99+
; CHECK-NEXT: v_accvgpr_read_b32 v29, a1
100+
; CHECK-NEXT: v_accvgpr_read_b32 v28, a0
98101
; CHECK-NEXT: s_mov_b64 s[24:25], -1
99102
; CHECK-NEXT: s_mov_b64 s[8:9], -1
100103
; CHECK-NEXT: s_mov_b64 vcc, s[2:3]
101-
; CHECK-NEXT: ; implicit-def: $agpr2_agpr3
104+
; CHECK-NEXT: ; implicit-def: $agpr0_agpr1
102105
; CHECK-NEXT: s_cbranch_vccz .LBB0_5
103106
; CHECK-NEXT: ; %bb.7: ; %.lr.ph2070.i.i.i3291
104107
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
105-
; CHECK-NEXT: v_accvgpr_mov_b32 a3, a1
106-
; CHECK-NEXT: v_accvgpr_mov_b32 a2, a0
108+
; CHECK-NEXT: v_accvgpr_write_b32 a0, v30
109+
; CHECK-NEXT: v_accvgpr_write_b32 a1, v31
107110
; CHECK-NEXT: s_mov_b64 s[8:9], s[18:19]
108111
; CHECK-NEXT: s_mov_b64 vcc, s[6:7]
109112
; CHECK-NEXT: s_cbranch_vccz .LBB0_5
110113
; CHECK-NEXT: ; %bb.8: ; %.preheader1856.preheader.i.i.i3325
111114
; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
112-
; CHECK-NEXT: v_accvgpr_write_b32 a2, v26
115+
; CHECK-NEXT: v_accvgpr_write_b32 a0, v26
113116
; CHECK-NEXT: s_mov_b64 s[24:25], 0
114-
; CHECK-NEXT: v_accvgpr_write_b32 a3, v27
117+
; CHECK-NEXT: v_accvgpr_write_b32 a1, v27
115118
; CHECK-NEXT: s_mov_b64 s[8:9], 0
116119
; CHECK-NEXT: s_branch .LBB0_5
117120
; CHECK-NEXT: .LBB0_9: ; in Loop: Header=BB0_2 Depth=1
118-
; CHECK-NEXT: v_mov_b64_e32 v[24:25], s[10:11]
119-
; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
120121
; CHECK-NEXT: s_mov_b64 s[22:23], 0
121-
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
122+
; CHECK-NEXT: v_mov_b64_e32 v[30:31], s[10:11]
122123
; CHECK-NEXT: s_mov_b64 s[8:9], s[20:21]
123124
; CHECK-NEXT: s_branch .LBB0_15
124125
; CHECK-NEXT: .LBB0_10: ; in Loop: Header=BB0_2 Depth=1
@@ -135,21 +136,19 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
135136
; CHECK-NEXT: v_cndmask_b32_e64 v23, v23, 0, s[16:17]
136137
; CHECK-NEXT: v_cndmask_b32_e64 v22, v22, 0, s[16:17]
137138
; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[8:9]
138-
; CHECK-NEXT: s_and_b64 s[8:9], exec, s[16:17]
139139
; CHECK-NEXT: v_mov_b32_e32 v17, v16
140+
; CHECK-NEXT: s_and_b64 s[8:9], exec, s[16:17]
141+
; CHECK-NEXT: global_store_dwordx2 v20, v[16:17], s[12:13]
140142
; CHECK-NEXT: s_cselect_b32 s23, s23, 0
141143
; CHECK-NEXT: s_cselect_b32 s22, s22, 0
142144
; CHECK-NEXT: s_mov_b64 s[8:9], -1
143-
; CHECK-NEXT: global_store_dwordx2 v0, v[16:17], s[12:13]
144145
; CHECK-NEXT: s_branch .LBB0_14
145146
; CHECK-NEXT: .LBB0_13: ; in Loop: Header=BB0_2 Depth=1
146147
; CHECK-NEXT: s_mov_b64 s[8:9], 0
147148
; CHECK-NEXT: v_mov_b64_e32 v[22:23], 0
148-
; CHECK-NEXT: .LBB0_14: ; %Flow8
149+
; CHECK-NEXT: .LBB0_14: ; %Flow6
149150
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
150-
; CHECK-NEXT: v_accvgpr_write_b32 a0, v24
151-
; CHECK-NEXT: v_mov_b64_e32 v[16:17], 0
152-
; CHECK-NEXT: v_accvgpr_write_b32 a1, v25
151+
; CHECK-NEXT: v_mov_b64_e32 v[30:31], v[24:25]
153152
; CHECK-NEXT: .LBB0_15: ; %Flow6
154153
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
155154
; CHECK-NEXT: s_mov_b64 s[24:25], -1
@@ -158,7 +157,7 @@ define amdgpu_kernel void @vgpr_mfma_pass_av_split_crash(double %arg1, i1 %arg2,
158157
; CHECK-NEXT: ; %bb.16: ; %._crit_edge2105.i.i.i2330
159158
; CHECK-NEXT: ; in Loop: Header=BB0_2 Depth=1
160159
; CHECK-NEXT: s_mov_b64 s[24:25], 0
161-
; CHECK-NEXT: global_store_dwordx2 v0, v[16:17], s[12:13]
160+
; CHECK-NEXT: global_store_dwordx2 v20, v[20:21], s[12:13]
162161
; CHECK-NEXT: s_branch .LBB0_1
163162
; CHECK-NEXT: .LBB0_17: ; %DummyReturnBlock
164163
; CHECK-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/flat-scratch.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4152,7 +4152,8 @@ define void @store_load_i64_aligned(ptr addrspace(5) nocapture %arg) {
41524152
; GFX942-LABEL: store_load_i64_aligned:
41534153
; GFX942: ; %bb.0: ; %bb
41544154
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4155-
; GFX942-NEXT: v_mov_b64_e32 v[2:3], 15
4155+
; GFX942-NEXT: v_mov_b32_e32 v2, 15
4156+
; GFX942-NEXT: v_mov_b32_e32 v3, 0
41564157
; GFX942-NEXT: scratch_store_dwordx2 v0, v[2:3], off sc0 sc1
41574158
; GFX942-NEXT: s_waitcnt vmcnt(0)
41584159
; GFX942-NEXT: scratch_load_dwordx2 v[0:1], v0, off sc0 sc1
@@ -4262,7 +4263,8 @@ define void @store_load_i64_unaligned(ptr addrspace(5) nocapture %arg) {
42624263
; GFX942-LABEL: store_load_i64_unaligned:
42634264
; GFX942: ; %bb.0: ; %bb
42644265
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
4265-
; GFX942-NEXT: v_mov_b64_e32 v[2:3], 15
4266+
; GFX942-NEXT: v_mov_b32_e32 v2, 15
4267+
; GFX942-NEXT: v_mov_b32_e32 v3, 0
42664268
; GFX942-NEXT: scratch_store_dwordx2 v0, v[2:3], off sc0 sc1
42674269
; GFX942-NEXT: s_waitcnt vmcnt(0)
42684270
; GFX942-NEXT: scratch_load_dwordx2 v[0:1], v0, off sc0 sc1

‎llvm/test/CodeGen/AMDGPU/imm.ll‎

Lines changed: 26 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1969,9 +1969,10 @@ define amdgpu_kernel void @add_inline_imm_neg_1_f64(ptr addrspace(1) %out, [8 x
19691969
; GFX942-LABEL: add_inline_imm_neg_1_f64:
19701970
; GFX942: ; %bb.0:
19711971
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
1972+
; GFX942-NEXT: v_mov_b32_e32 v0, -1
19721973
; GFX942-NEXT: s_mov_b32 s3, 0xf000
19731974
; GFX942-NEXT: s_mov_b32 s2, -1
1974-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -1
1975+
; GFX942-NEXT: v_mov_b32_e32 v1, v0
19751976
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
19761977
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
19771978
; GFX942-NEXT: s_endpgm
@@ -2008,7 +2009,8 @@ define amdgpu_kernel void @add_inline_imm_neg_2_f64(ptr addrspace(1) %out, [8 x
20082009
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
20092010
; GFX942-NEXT: s_mov_b32 s3, 0xf000
20102011
; GFX942-NEXT: s_mov_b32 s2, -1
2011-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -2
2012+
; GFX942-NEXT: v_mov_b32_e32 v0, -2
2013+
; GFX942-NEXT: v_mov_b32_e32 v1, -1
20122014
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
20132015
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
20142016
; GFX942-NEXT: s_endpgm
@@ -2045,7 +2047,8 @@ define amdgpu_kernel void @add_inline_imm_neg_16_f64(ptr addrspace(1) %out, [8 x
20452047
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
20462048
; GFX942-NEXT: s_mov_b32 s3, 0xf000
20472049
; GFX942-NEXT: s_mov_b32 s2, -1
2048-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -16
2050+
; GFX942-NEXT: v_mov_b32_e32 v0, -16
2051+
; GFX942-NEXT: v_mov_b32_e32 v1, -1
20492052
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
20502053
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
20512054
; GFX942-NEXT: s_endpgm
@@ -2160,9 +2163,10 @@ define amdgpu_kernel void @store_inline_imm_0.0_f64(ptr addrspace(1) %out) {
21602163
; GFX942-LABEL: store_inline_imm_0.0_f64:
21612164
; GFX942: ; %bb.0:
21622165
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
2166+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
21632167
; GFX942-NEXT: s_mov_b32 s3, 0xf000
21642168
; GFX942-NEXT: s_mov_b32 s2, -1
2165-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 0
2169+
; GFX942-NEXT: v_mov_b32_e32 v1, v0
21662170
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
21672171
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
21682172
; GFX942-NEXT: s_endpgm
@@ -2235,7 +2239,8 @@ define amdgpu_kernel void @store_inline_imm_0.5_f64(ptr addrspace(1) %out) {
22352239
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
22362240
; GFX942-NEXT: s_mov_b32 s3, 0xf000
22372241
; GFX942-NEXT: s_mov_b32 s2, -1
2238-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 0.5
2242+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2243+
; GFX942-NEXT: v_mov_b32_e32 v1, 0x3fe00000
22392244
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
22402245
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
22412246
; GFX942-NEXT: s_endpgm
@@ -2271,7 +2276,8 @@ define amdgpu_kernel void @store_inline_imm_m_0.5_f64(ptr addrspace(1) %out) {
22712276
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
22722277
; GFX942-NEXT: s_mov_b32 s3, 0xf000
22732278
; GFX942-NEXT: s_mov_b32 s2, -1
2274-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -0.5
2279+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2280+
; GFX942-NEXT: v_mov_b32_e32 v1, 0xbfe00000
22752281
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
22762282
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
22772283
; GFX942-NEXT: s_endpgm
@@ -2307,7 +2313,8 @@ define amdgpu_kernel void @store_inline_imm_1.0_f64(ptr addrspace(1) %out) {
23072313
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
23082314
; GFX942-NEXT: s_mov_b32 s3, 0xf000
23092315
; GFX942-NEXT: s_mov_b32 s2, -1
2310-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 1.0
2316+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2317+
; GFX942-NEXT: v_mov_b32_e32 v1, 0x3ff00000
23112318
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
23122319
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
23132320
; GFX942-NEXT: s_endpgm
@@ -2343,7 +2350,8 @@ define amdgpu_kernel void @store_inline_imm_m_1.0_f64(ptr addrspace(1) %out) {
23432350
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
23442351
; GFX942-NEXT: s_mov_b32 s3, 0xf000
23452352
; GFX942-NEXT: s_mov_b32 s2, -1
2346-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -1.0
2353+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2354+
; GFX942-NEXT: v_mov_b32_e32 v1, 0xbff00000
23472355
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
23482356
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
23492357
; GFX942-NEXT: s_endpgm
@@ -2379,7 +2387,8 @@ define amdgpu_kernel void @store_inline_imm_2.0_f64(ptr addrspace(1) %out) {
23792387
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
23802388
; GFX942-NEXT: s_mov_b32 s3, 0xf000
23812389
; GFX942-NEXT: s_mov_b32 s2, -1
2382-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 2.0
2390+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2391+
; GFX942-NEXT: v_mov_b32_e32 v1, 2.0
23832392
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
23842393
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
23852394
; GFX942-NEXT: s_endpgm
@@ -2415,7 +2424,8 @@ define amdgpu_kernel void @store_inline_imm_m_2.0_f64(ptr addrspace(1) %out) {
24152424
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
24162425
; GFX942-NEXT: s_mov_b32 s3, 0xf000
24172426
; GFX942-NEXT: s_mov_b32 s2, -1
2418-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -2.0
2427+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2428+
; GFX942-NEXT: v_mov_b32_e32 v1, -2.0
24192429
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
24202430
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
24212431
; GFX942-NEXT: s_endpgm
@@ -2451,7 +2461,8 @@ define amdgpu_kernel void @store_inline_imm_4.0_f64(ptr addrspace(1) %out) {
24512461
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
24522462
; GFX942-NEXT: s_mov_b32 s3, 0xf000
24532463
; GFX942-NEXT: s_mov_b32 s2, -1
2454-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 4.0
2464+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2465+
; GFX942-NEXT: v_mov_b32_e32 v1, 0x40100000
24552466
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
24562467
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
24572468
; GFX942-NEXT: s_endpgm
@@ -2487,7 +2498,8 @@ define amdgpu_kernel void @store_inline_imm_m_4.0_f64(ptr addrspace(1) %out) {
24872498
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
24882499
; GFX942-NEXT: s_mov_b32 s3, 0xf000
24892500
; GFX942-NEXT: s_mov_b32 s2, -1
2490-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], -4.0
2501+
; GFX942-NEXT: v_mov_b32_e32 v0, 0
2502+
; GFX942-NEXT: v_mov_b32_e32 v1, 0xc0100000
24912503
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
24922504
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
24932505
; GFX942-NEXT: s_endpgm
@@ -2523,7 +2535,8 @@ define amdgpu_kernel void @store_inv_2pi_f64(ptr addrspace(1) %out) {
25232535
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
25242536
; GFX942-NEXT: s_mov_b32 s3, 0xf000
25252537
; GFX942-NEXT: s_mov_b32 s2, -1
2526-
; GFX942-NEXT: v_mov_b64_e32 v[0:1], 0.15915494309189532
2538+
; GFX942-NEXT: v_mov_b32_e32 v0, 0x6dc9c882
2539+
; GFX942-NEXT: v_mov_b32_e32 v1, 0x3fc45f30
25272540
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
25282541
; GFX942-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
25292542
; GFX942-NEXT: s_endpgm

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