[llvm][CodeGen] Modifications made based on review comments 1

Author: huaatian

llvm/include/llvm/CodeGen/ModuloSchedule.h

@@ -188,8 +188,8 @@ class ModuloScheduleExpander {
   /// Instructions to change when emitting the final schedule.
   InstrChangesTy InstrChanges;
 
-  /// Record newly created registers with empty live intervals.
-  SmallVector<Register> EmptyIntervalRegs;
+  /// Record the registers that need to compute live intervals.
+  SmallVector<Register> NoIntervalRegs;
 
   void generatePipelinedLoop();
   void generateProlog(unsigned LastStage, MachineBasicBlock *KernelBB,
@@ -214,7 +214,7 @@ class ModuloScheduleExpander {
   void addBranches(MachineBasicBlock &PreheaderBB, MBBVectorTy &PrologBBs,
                    MachineBasicBlock *KernelBB, MBBVectorTy &EpilogBBs,
                    ValueMapTy *VRMap);
-  void recalcEmptyIntervals();
+  void calculateIntervals();
   bool computeDelta(MachineInstr &MI, unsigned &Delta);
   void updateMemOperands(MachineInstr &NewMI, MachineInstr &OldMI,
                          unsigned Num);

llvm/lib/CodeGen/ModuloSchedule.cpp

@@ -181,7 +181,9 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
   // Add branches between prolog and epilog blocks.
   addBranches(*Preheader, PrologBBs, KernelBB, EpilogBBs, VRMap);
 
-  recalcEmptyIntervals();
+  // The intervals of newly created virtual registers are calculated after the
+  // kernel expansion.
+  calculateIntervals();
 
   delete[] VRMap;
   delete[] VRMapPhi;
@@ -351,15 +353,15 @@ static void replaceRegUsesAfterLoop(Register FromReg, Register ToReg,
                                     MachineBasicBlock *MBB,
                                     MachineRegisterInfo &MRI,
                                     LiveIntervals &LIS,
-                                    SmallVector<Register> &EmptyIntervalRegs) {
+                                    SmallVector<Register> &NoIntervalRegs) {
   for (MachineOperand &O :
        llvm::make_early_inc_range(MRI.use_operands(FromReg)))
     if (O.getParent()->getParent() != MBB)
       O.setReg(ToReg);
-  if (!LIS.hasInterval(ToReg)) {
-    LIS.createEmptyInterval(ToReg);
-    EmptyIntervalRegs.push_back(ToReg);
-  }
+  // The interval will be calculated after the kernel expansion in
+  // calculateIntervals().
+  if (!LIS.hasInterval(ToReg))
+    NoIntervalRegs.push_back(ToReg);
 }
 
 /// Return true if the register has a use that occurs outside the
@@ -552,7 +554,7 @@ void ModuloScheduleExpander::generateExistingPhis(
 
               if (IsLast && np == NumPhis - 1)
                 replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS,
-                                        EmptyIntervalRegs);
+                                        NoIntervalRegs);
               continue;
             }
           }
@@ -593,7 +595,7 @@ void ModuloScheduleExpander::generateExistingPhis(
       // register to replace depends on whether the Phi is scheduled in the
       // epilog.
       if (IsLast && np == NumPhis - 1)
-        replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS, EmptyIntervalRegs);
+        replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS, NoIntervalRegs);
 
       // In the kernel, a dependent Phi uses the value from this Phi.
       if (InKernel)
@@ -613,8 +615,7 @@ void ModuloScheduleExpander::generateExistingPhis(
     if (NumStages == 0 && IsLast) {
       auto It = VRMap[CurStageNum].find(LoopVal);
       if (It != VRMap[CurStageNum].end())
-        replaceRegUsesAfterLoop(Def, It->second, BB, MRI, LIS,
-                                EmptyIntervalRegs);
+        replaceRegUsesAfterLoop(Def, It->second, BB, MRI, LIS, NoIntervalRegs);
     }
   }
 }
@@ -735,7 +736,7 @@ void ModuloScheduleExpander::generatePhis(
                                   NewReg);
         }
         if (IsLast && np == NumPhis - 1)
-          replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS, EmptyIntervalRegs);
+          replaceRegUsesAfterLoop(Def, NewReg, BB, MRI, LIS, NoIntervalRegs);
       }
     }
   }
@@ -947,23 +948,24 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
   }
 }
 
-/// Some new registers are generated during the kernel expansion. We recalculate
-/// the live intervals of these registers after the expansion.
-void ModuloScheduleExpander::recalcEmptyIntervals() {
-  // The interval can be computed if the register's non-debug users have
+/// Some registers are generated during the kernel expansion. We calculate the
+/// live intervals of these registers after the expansion.
+void ModuloScheduleExpander::calculateIntervals() {
+  // The interval can be computed if all the register's non-debug users have
   // slot indexes.
-  auto CanRecalculateInterval = [this](unsigned Reg) -> bool {
+  auto CanCalculateInterval = [this](Register Reg) -> bool {
     for (auto &Opnd : this->MRI.reg_nodbg_operands(Reg))
       if (this->LIS.isNotInMIMap(*Opnd.getParent()))
         return false;
     return true;
   };
-  for (auto Reg : EmptyIntervalRegs)
-    if (CanRecalculateInterval(Reg)) {
-      LIS.removeInterval(Reg);
+  for (auto Reg : NoIntervalRegs) {
+    if (CanCalculateInterval(Reg))
       LIS.createAndComputeVirtRegInterval(Reg);
-    }
-  EmptyIntervalRegs.clear();
+    else
+      LIS.createEmptyInterval(Reg);
+  }
+  NoIntervalRegs.clear();
 }
 
 /// Return true if we can compute the amount the instruction changes
@@ -1087,7 +1089,7 @@ void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
       MO.setReg(NewReg);
       VRMap[CurStageNum][reg] = NewReg;
       if (LastDef)
-        replaceRegUsesAfterLoop(reg, NewReg, BB, MRI, LIS, EmptyIntervalRegs);
+        replaceRegUsesAfterLoop(reg, NewReg, BB, MRI, LIS, NoIntervalRegs);
     } else if (MO.isUse()) {
       MachineInstr *Def = MRI.getVRegDef(reg);
       // Compute the stage that contains the last definition for instruction.