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Wolfram70Wolfram70
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[MLIR][NVVM] Update convert Ops to use builtin types (#159704)
This change updates the `convert.f32x2.to.f6x2`, `convert.f32x2.to.f8x2`, `convert.f16x2.to.f8x2`, and `convert.bf16x2.to.f8x2` Ops to use builtin types for the destination types as a `TypeAttr` instead of custom enums. The corresponding tests are updated to reflect the changes in the assembly format.
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5 files changed

+180
-144
lines changed

5 files changed

+180
-144
lines changed

‎mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td‎

Lines changed: 20 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
2222
include "mlir/Dialect/LLVMIR/BasicPtxBuilderInterface.td"
2323
include "mlir/Interfaces/InferIntRangeInterface.td"
2424
include "mlir/Dialect/LLVMIR/LLVMTypes.td"
25+
include "mlir/IR/CommonAttrConstraints.td"
2526

2627
def LLVM_PointerGeneric : LLVM_PointerInAddressSpace<0>;
2728
def LLVM_PointerGlobal : LLVM_PointerInAddressSpace<1>;
@@ -1654,18 +1655,6 @@ def NVVM_ConvertFloatToTF32Op : NVVM_Op<"convert.float.to.tf32"> {
16541655
}];
16551656
}
16561657

1657-
def ConvertFP6E2M3 : I32EnumAttrCase<"E2M3", 0, "e2m3">;
1658-
def ConvertFP6E3M2 : I32EnumAttrCase<"E3M2", 1, "e3m2">;
1659-
1660-
def ConvertFP6Type : I32EnumAttr<"ConvertFP6Type", "NVVM ConvertFP6Type kind",
1661-
[ConvertFP6E2M3, ConvertFP6E3M2]> {
1662-
let genSpecializedAttr = 0;
1663-
let cppNamespace = "::mlir::NVVM";
1664-
}
1665-
def ConvertFP6TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP6Type, "convert_fp6_type"> {
1666-
let assemblyFormat = "`<` $value `>`";
1667-
}
1668-
16691658
def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
16701659
let summary = "Convert a pair of float inputs to f6x2";
16711660
let description = [{
@@ -1686,19 +1675,20 @@ def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
16861675

16871676
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
16881677
let arguments = (ins
1689-
ConvertFP6TypeAttr:$type,
16901678
F32:$a,
16911679
F32:$b,
1692-
DefaultValuedAttr<BoolAttr, "false">:$relu);
1693-
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
1680+
DefaultValuedAttr<BoolAttr, "false">:$relu,
1681+
TypeAttr:$dstTy);
1682+
let assemblyFormat = "$a `,` $b attr-dict `:` type($dst) `(` $dstTy `)`";
1683+
let hasVerifier = 1;
16941684

16951685
let extraClassDeclaration = [{
1696-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP6Type,
1686+
static llvm::Intrinsic::ID getIntrinsicID(mlir::Type dstTy,
16971687
bool hasRelu);
16981688
}];
16991689

17001690
string llvmBuilder = [{
1701-
auto intId = NVVM::ConvertF32x2ToF6x2Op::getIntrinsicID($type, $relu);
1691+
auto intId = NVVM::ConvertF32x2ToF6x2Op::getIntrinsicID($dstTy, $relu);
17021692
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
17031693
if(op.getDst().getType().isInteger(16))
17041694
$dst = packedI16;
@@ -1708,19 +1698,6 @@ def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
17081698
}];
17091699
}
17101700

1711-
def ConvertFP8E4M3 : I32EnumAttrCase<"E4M3", 0, "e4m3">;
1712-
def ConvertFP8E5M2 : I32EnumAttrCase<"E5M2", 1, "e5m2">;
1713-
def ConvertFP8UE8M0 : I32EnumAttrCase<"UE8M0", 2, "ue8m0">;
1714-
1715-
def ConvertFP8Type : I32EnumAttr<"ConvertFP8Type", "NVVM ConvertFP8Type kind",
1716-
[ConvertFP8E4M3, ConvertFP8E5M2, ConvertFP8UE8M0]> {
1717-
let genSpecializedAttr = 0;
1718-
let cppNamespace = "::mlir::NVVM";
1719-
}
1720-
def ConvertFP8TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP8Type, "convert_fp8_type"> {
1721-
let assemblyFormat = "`<` $value `>`";
1722-
}
1723-
17241701
def NVVM_ConvertF32x2ToF8x2Op : NVVM_Op<"convert.f32x2.to.f8x2"> {
17251702
let summary = "Convert a pair of float inputs to f8x2";
17261703
let description = [{
@@ -1742,23 +1719,23 @@ def NVVM_ConvertF32x2ToF8x2Op : NVVM_Op<"convert.f32x2.to.f8x2"> {
17421719
let hasVerifier = 1;
17431720
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
17441721
let arguments = (ins
1745-
ConvertFP8TypeAttr:$type,
17461722
F32:$a,
17471723
F32:$b,
17481724
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
17491725
DefaultValuedAttr<SaturationModeAttr, "SaturationMode::NONE">:$sat,
1750-
DefaultValuedAttr<BoolAttr, "false">:$relu);
1751-
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
1726+
DefaultValuedAttr<BoolAttr, "false">:$relu,
1727+
TypeAttr:$dstTy);
1728+
let assemblyFormat = "$a `,` $b attr-dict `:` type($dst) `(` $dstTy `)`";
17521729

17531730
let extraClassDeclaration = [{
1754-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
1731+
static llvm::Intrinsic::ID getIntrinsicID(mlir::Type dstTy,
17551732
NVVM::FPRoundingMode rnd,
17561733
NVVM::SaturationMode sat,
17571734
bool hasRelu);
17581735
}];
17591736

17601737
string llvmBuilder = [{
1761-
auto intId = NVVM::ConvertF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
1738+
auto intId = NVVM::ConvertF32x2ToF8x2Op::getIntrinsicID($dstTy, $rnd, $sat, $relu);
17621739
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
17631740
if(op.getDst().getType().isInteger(16))
17641741
$dst = packedI16;
@@ -1790,18 +1767,18 @@ def NVVM_ConvertF16x2ToF8x2Op : NVVM_Op<"convert.f16x2.to.f8x2"> {
17901767
let hasVerifier = 1;
17911768
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
17921769
let arguments = (ins
1793-
ConvertFP8TypeAttr:$type,
17941770
VectorOfLengthAndType<[2], [F16]>:$a,
1795-
DefaultValuedAttr<BoolAttr, "false">:$relu);
1796-
let assemblyFormat = "$type $a attr-dict `:` type($a) `->` type($dst)";
1771+
DefaultValuedAttr<BoolAttr, "false">:$relu,
1772+
TypeAttr:$dstTy);
1773+
let assemblyFormat = "$a attr-dict `:` type($a) `->` type($dst) `(` $dstTy `)`";
17971774

17981775
let extraClassDeclaration = [{
1799-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
1776+
static llvm::Intrinsic::ID getIntrinsicID(mlir::Type dstTy,
18001777
bool hasRelu);
18011778
}];
18021779

18031780
string llvmBuilder = [{
1804-
auto intId = NVVM::ConvertF16x2ToF8x2Op::getIntrinsicID($type, $relu);
1781+
auto intId = NVVM::ConvertF16x2ToF8x2Op::getIntrinsicID($dstTy, $relu);
18051782
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
18061783
if(op.getDst().getType().isInteger(16))
18071784
$dst = packedI16;
@@ -1833,11 +1810,11 @@ def NVVM_ConvertBF16x2ToF8x2Op : NVVM_Op<"convert.bf16x2.to.f8x2"> {
18331810
let hasVerifier = 1;
18341811
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
18351812
let arguments = (ins
1836-
ConvertFP8TypeAttr:$type,
18371813
VectorOfLengthAndType<[2], [BF16]>:$a,
18381814
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
1839-
DefaultValuedAttr<SaturationModeAttr, "SaturationMode::NONE">:$sat);
1840-
let assemblyFormat = "$type $a attr-dict `:` type($a) `->` type($dst)";
1815+
DefaultValuedAttr<SaturationModeAttr, "SaturationMode::NONE">:$sat,
1816+
TypeAttr:$dstTy);
1817+
let assemblyFormat = "$a attr-dict `:` type($a) `->` type($dst) `(` $dstTy `)`";
18411818

18421819
let extraClassDeclaration = [{
18431820
static llvm::Intrinsic::ID getIntrinsicID(NVVM::FPRoundingMode rnd,

‎mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp‎

Lines changed: 109 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,18 @@ LogicalResult ConvertFloatToTF32Op::verify() {
216216
return success();
217217
}
218218

219+
LogicalResult ConvertF32x2ToF6x2Op::verify() {
220+
mlir::MLIRContext *ctx = getContext();
221+
222+
if (!llvm::isa<mlir::Float6E2M3FNType, mlir::Float6E3M2FNType>(getDstTy())) {
223+
return emitOpError("Only ")
224+
<< mlir::Float6E2M3FNType::get(ctx) << " and "
225+
<< mlir::Float6E3M2FNType::get(ctx)
226+
<< " types are supported for conversions from f32x2 to f6x2.";
227+
}
228+
return success();
229+
}
230+
219231
LogicalResult ConvertF32x2ToF8x2Op::verify() {
220232
using RndMode = NVVM::FPRoundingMode;
221233
using SatMode = NVVM::SaturationMode;
@@ -227,41 +239,67 @@ LogicalResult ConvertF32x2ToF8x2Op::verify() {
227239

228240
bool hasRelu = getRelu();
229241

230-
switch (getType()) {
231-
case ConvertFP8Type::E4M3:
232-
case ConvertFP8Type::E5M2:
233-
if (!isRoundingModeRN)
234-
return emitOpError("Only RN rounding mode is supported for conversions "
235-
"from f32x2 to .e4m3x2 or .e5m2x2 types");
236-
if (!isSatFinite)
237-
return emitOpError("Only SATFINITE saturation mode is supported for "
238-
"conversions from f32x2 to .e4m3x2 or .e5m2x2 types");
239-
break;
240-
case ConvertFP8Type::UE8M0:
241-
if (!(isRoundingModeRZ || isRoundingModeRP))
242-
return emitOpError("Only RZ or RP rounding modes are supported for "
243-
"conversions from f32x2 to .ue8m0x2 type");
244-
if (hasRelu)
245-
return emitOpError("relu not supported for conversions to .ue8m0x2 type");
246-
break;
247-
}
248-
return success();
242+
mlir::MLIRContext *ctx = getContext();
243+
244+
return llvm::TypeSwitch<mlir::Type, LogicalResult>(getDstTy())
245+
.Case<mlir::Float8E4M3FNType, mlir::Float8E5M2Type>(
246+
[&](mlir::Type) -> LogicalResult {
247+
if (!isRoundingModeRN) {
248+
return emitOpError("Only RN rounding mode is supported for "
249+
"conversions from f32x2 to ")
250+
<< mlir::Float8E4M3FNType::get(ctx) << " and "
251+
<< mlir::Float8E5M2Type::get(ctx) << " types";
252+
}
253+
if (!isSatFinite) {
254+
return emitOpError("Only SATFINITE saturation mode is supported "
255+
"for conversions "
256+
"from f32x2 to ")
257+
<< mlir::Float8E4M3FNType::get(ctx) << " and "
258+
<< mlir::Float8E5M2Type::get(ctx) << " types";
259+
}
260+
return success();
261+
})
262+
.Case<mlir::Float8E8M0FNUType>([&](mlir::Type) -> LogicalResult {
263+
if (!(isRoundingModeRZ || isRoundingModeRP)) {
264+
return emitOpError("Only RZ and RP rounding modes are supported for "
265+
"conversions from f32x2 to ")
266+
<< mlir::Float8E8M0FNUType::get(ctx) << " type";
267+
}
268+
if (hasRelu) {
269+
return emitOpError("relu not supported for conversions to ")
270+
<< mlir::Float8E8M0FNUType::get(ctx) << " type";
271+
}
272+
return success();
273+
})
274+
.Default([&](mlir::Type) {
275+
return emitOpError("Only ")
276+
<< mlir::Float8E4M3FNType::get(ctx) << ", "
277+
<< mlir::Float8E5M2Type::get(ctx) << ", and "
278+
<< mlir::Float8E8M0FNUType::get(ctx)
279+
<< " types are "
280+
"supported for conversions from f32x2 to f8x2";
281+
});
249282
}
250283

251284
LogicalResult ConvertF16x2ToF8x2Op::verify() {
252-
if (getType() == ConvertFP8Type::UE8M0)
253-
return emitOpError("Only .e4m3 or .e5m2 types are supported for "
254-
"conversions from f16x2 to f8x2.");
285+
mlir::MLIRContext *ctx = getContext();
255286

287+
if (!llvm::isa<mlir::Float8E4M3FNType, mlir::Float8E5M2Type>(getDstTy())) {
288+
return emitOpError("Only ")
289+
<< mlir::Float8E4M3FNType::get(ctx) << " and "
290+
<< mlir::Float8E5M2Type::get(ctx)
291+
<< " types are supported for conversions from f16x2 to f8x2.";
292+
}
256293
return success();
257294
}
258295

259296
LogicalResult ConvertBF16x2ToF8x2Op::verify() {
260297
using RndMode = NVVM::FPRoundingMode;
261298

262-
if (getType() != ConvertFP8Type::UE8M0)
263-
return emitOpError(
264-
"Only .ue8m0 type is supported for conversions from bf16x2 to f8x2.");
299+
if (!llvm::isa<mlir::Float8E8M0FNUType>(getDstTy()))
300+
return emitOpError("Only ") << mlir::Float8E8M0FNUType::get(getContext())
301+
<< " type is supported for conversions from "
302+
"bf16x2 to f8x2.";
265303

266304
auto rnd = getRnd();
267305
if (!(rnd == RndMode::RZ || rnd == RndMode::RP))
@@ -1980,15 +2018,19 @@ ConvertFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
19802018
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu_satfinite \
19812019
: llvm::Intrinsic::nvvm_ff_to_##type##_rn_satfinite
19822020

1983-
llvm::Intrinsic::ID
1984-
ConvertF32x2ToF6x2Op::getIntrinsicID(NVVM::ConvertFP6Type type, bool hasRelu) {
1985-
switch (type) {
1986-
case NVVM::ConvertFP6Type::E2M3:
1987-
return GET_F32x2_TO_F6x2_ID(e2m3x2, hasRelu);
1988-
case NVVM::ConvertFP6Type::E3M2:
1989-
return GET_F32x2_TO_F6x2_ID(e3m2x2, hasRelu);
1990-
}
1991-
llvm_unreachable("Invalid conversion in ConvertF32x2ToF6x2Op");
2021+
llvm::Intrinsic::ID ConvertF32x2ToF6x2Op::getIntrinsicID(mlir::Type dstTy,
2022+
bool hasRelu) {
2023+
return llvm::TypeSwitch<mlir::Type, llvm::Intrinsic::ID>(dstTy)
2024+
.Case<mlir::Float6E2M3FNType>([&](mlir::Float6E2M3FNType) {
2025+
return GET_F32x2_TO_F6x2_ID(e2m3x2, hasRelu);
2026+
})
2027+
.Case<mlir::Float6E3M2FNType>([&](mlir::Float6E3M2FNType) {
2028+
return GET_F32x2_TO_F6x2_ID(e3m2x2, hasRelu);
2029+
})
2030+
.Default([](mlir::Type) {
2031+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF6x2Op");
2032+
return llvm::Intrinsic::not_intrinsic;
2033+
});
19922034
}
19932035

19942036
#define GET_F32x2_TO_F8X2_US_ID(rnd, has_satf) \
@@ -2000,41 +2042,50 @@ ConvertF32x2ToF6x2Op::getIntrinsicID(NVVM::ConvertFP6Type type, bool hasRelu) {
20002042
: llvm::Intrinsic::nvvm_ff_to_##type##_rn
20012043

20022044
llvm::Intrinsic::ID
2003-
ConvertF32x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type,
2004-
NVVM::FPRoundingMode rnd,
2045+
ConvertF32x2ToF8x2Op::getIntrinsicID(mlir::Type dstTy, NVVM::FPRoundingMode rnd,
20052046
NVVM::SaturationMode sat, bool hasRelu) {
20062047
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
20072048
bool hasRoundingModeRZ = (rnd == NVVM::FPRoundingMode::RZ);
20082049
bool hasRoundingModeRP = (rnd == NVVM::FPRoundingMode::RP);
20092050

2010-
switch (type) {
2011-
case NVVM::ConvertFP8Type::E4M3:
2012-
return GET_F32x2_TO_F8X2_S_ID(e4m3x2, hasRelu);
2013-
case NVVM::ConvertFP8Type::E5M2:
2014-
return GET_F32x2_TO_F8X2_S_ID(e5m2x2, hasRelu);
2015-
case NVVM::ConvertFP8Type::UE8M0:
2016-
if (hasRoundingModeRZ)
2017-
return GET_F32x2_TO_F8X2_US_ID(rz, hasSatFinite);
2018-
else if (hasRoundingModeRP)
2019-
return GET_F32x2_TO_F8X2_US_ID(rp, hasSatFinite);
2020-
}
2021-
llvm_unreachable("Invalid conversion in CvtFloatToF8x2Op");
2051+
return llvm::TypeSwitch<mlir::Type, llvm::Intrinsic::ID>(dstTy)
2052+
.Case<mlir::Float8E4M3FNType>([&](mlir::Float8E4M3FNType) {
2053+
return GET_F32x2_TO_F8X2_S_ID(e4m3x2, hasRelu);
2054+
})
2055+
.Case<mlir::Float8E5M2Type>([&](mlir::Float8E5M2Type) {
2056+
return GET_F32x2_TO_F8X2_S_ID(e5m2x2, hasRelu);
2057+
})
2058+
.Case<mlir::Float8E8M0FNUType>([&](mlir::Float8E8M0FNUType) {
2059+
if (hasRoundingModeRZ)
2060+
return GET_F32x2_TO_F8X2_US_ID(rz, hasSatFinite);
2061+
else if (hasRoundingModeRP)
2062+
return GET_F32x2_TO_F8X2_US_ID(rp, hasSatFinite);
2063+
2064+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF8x2Op");
2065+
})
2066+
.Default([](mlir::Type) {
2067+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF8x2Op");
2068+
return llvm::Intrinsic::not_intrinsic;
2069+
});
20222070
}
20232071

20242072
#define GET_F16x2_TO_F8X2_ID(type, has_relu) \
20252073
has_relu ? llvm::Intrinsic::nvvm_f16x2_to_##type##_rn_relu \
20262074
: llvm::Intrinsic::nvvm_f16x2_to_##type##_rn
20272075

2028-
llvm::Intrinsic::ID
2029-
ConvertF16x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type, bool hasRelu) {
2030-
switch (type) {
2031-
case NVVM::ConvertFP8Type::E4M3:
2032-
return GET_F16x2_TO_F8X2_ID(e4m3x2, hasRelu);
2033-
case NVVM::ConvertFP8Type::E5M2:
2034-
return GET_F16x2_TO_F8X2_ID(e5m2x2, hasRelu);
2035-
default:
2036-
llvm_unreachable("Invalid ConvertFP8Type for CvtF16x2ToF8x2Op");
2037-
}
2076+
llvm::Intrinsic::ID ConvertF16x2ToF8x2Op::getIntrinsicID(mlir::Type dstTy,
2077+
bool hasRelu) {
2078+
return llvm::TypeSwitch<mlir::Type, llvm::Intrinsic::ID>(dstTy)
2079+
.Case<mlir::Float8E4M3FNType>([&](mlir::Float8E4M3FNType) {
2080+
return GET_F16x2_TO_F8X2_ID(e4m3x2, hasRelu);
2081+
})
2082+
.Case<mlir::Float8E5M2Type>([&](mlir::Float8E5M2Type) {
2083+
return GET_F16x2_TO_F8X2_ID(e5m2x2, hasRelu);
2084+
})
2085+
.Default([](mlir::Type) {
2086+
llvm_unreachable("Invalid conversion in ConvertF16x2ToF8x2Op");
2087+
return llvm::Intrinsic::not_intrinsic;
2088+
});
20382089
}
20392090

20402091
#define GET_BF16X2_TO_F8X2_ID(rnd, has_satf) \

‎mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
// CHECK-LABEL: @convert_f32x2_to_fp6x2_packed
44
llvm.func @convert_f32x2_to_fp6x2_packed(%srcA : f32, %srcB : f32) {
55
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
6-
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
6+
%res1 = nvvm.convert.f32x2.to.f6x2 %srcA, %srcB : i16 (f6E2M3FN)
77
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
8-
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
8+
%res2 = nvvm.convert.f32x2.to.f6x2 %srcA, %srcB : i16 (f6E3M2FN)
99
llvm.return
1010
}
1111

1212
// CHECK-LABEL: @convert_f32x2_to_fp6x2_vector
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llvm.func @convert_f32x2_to_fp6x2_vector(%srcA : f32, %srcB : f32) {
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//CHECK: %[[res0:.*]] = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
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//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res0]] to <2 x i8>
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%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
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%res1 = nvvm.convert.f32x2.to.f6x2 %srcA, %srcB : vector<2xi8> (f6E2M3FN)
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//CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
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//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
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%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
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%res2 = nvvm.convert.f32x2.to.f6x2 %srcA, %srcB : vector<2xi8> (f6E3M2FN)
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llvm.return
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}

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