Skip to content

Commit a60405c

Browse files
nikicnikic
committed
[LSR] Regenerate test checks (NFC)
1 parent 96bc07d commit a60405c

File tree

1 file changed

+209
-112
lines changed

1 file changed

+209
-112
lines changed

‎llvm/test/Transforms/LoopStrengthReduce/X86/bin_power.ll‎

Lines changed: 209 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,27 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt < %s -scalar-evolution-huge-expr-threshold=1000000 -loop-reduce -S | FileCheck %s
23

34
target datalayout = "e-m:e-i32:64-f80:128-n8:16:32:64-S128"
45
target triple = "x86_64-unknown-linux-gnu"
56

67
; Show that the b^2 is expanded correctly.
78
define i32 @test_01(i32 %a) {
8-
; CHECK-LABEL: @test_01
9-
; CHECK: entry:
10-
; CHECK-NEXT: br label %loop
11-
; CHECK: loop:
12-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
13-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
14-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
15-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
16-
; CHECK: exit:
17-
; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
18-
; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
19-
; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B2]], -1
20-
; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
21-
; CHECK-NEXT: ret i32 [[R2]]
9+
; CHECK-LABEL: define i32 @test_01(
10+
; CHECK-SAME: i32 [[A:%.*]]) {
11+
; CHECK-NEXT: [[ENTRY:.*]]:
12+
; CHECK-NEXT: br label %[[LOOP:.*]]
13+
; CHECK: [[LOOP]]:
14+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
15+
; CHECK-NEXT: [[B:%.*]] = add i32 [[A]], 1
16+
; CHECK-NEXT: [[B_POW_2:%.*]] = mul i32 [[B]], [[B]]
17+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
18+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
19+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
20+
; CHECK: [[EXIT]]:
21+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[B_POW_2]], -1
22+
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[LSR_IV_NEXT]]
23+
; CHECK-NEXT: ret i32 [[TMP1]]
24+
;
2225

2326
entry:
2427
br label %loop
@@ -38,22 +41,24 @@ exit: ; preds = %loop
3841

3942
; Show that b^8 is expanded correctly.
4043
define i32 @test_02(i32 %a) {
41-
; CHECK-LABEL: @test_02
42-
; CHECK: entry:
43-
; CHECK-NEXT: br label %loop
44-
; CHECK: loop:
45-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
46-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
47-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
48-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
49-
; CHECK: exit:
50-
; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
51-
; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
52-
; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
53-
; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
54-
; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B8]], -1
55-
; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
56-
; CHECK-NEXT: ret i32 [[R2]]
44+
; CHECK-LABEL: define i32 @test_02(
45+
; CHECK-SAME: i32 [[A:%.*]]) {
46+
; CHECK-NEXT: [[ENTRY:.*]]:
47+
; CHECK-NEXT: br label %[[LOOP:.*]]
48+
; CHECK: [[LOOP]]:
49+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
50+
; CHECK-NEXT: [[B:%.*]] = add i32 [[A]], 1
51+
; CHECK-NEXT: [[B_POW_2:%.*]] = mul i32 [[B]], [[B]]
52+
; CHECK-NEXT: [[B_POW_4:%.*]] = mul i32 [[B_POW_2]], [[B_POW_2]]
53+
; CHECK-NEXT: [[B_POW_8:%.*]] = mul i32 [[B_POW_4]], [[B_POW_4]]
54+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
55+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
56+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
57+
; CHECK: [[EXIT]]:
58+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[B_POW_8]], -1
59+
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[LSR_IV_NEXT]]
60+
; CHECK-NEXT: ret i32 [[TMP1]]
61+
;
5762
entry:
5863
br label %loop
5964

@@ -74,26 +79,29 @@ exit: ; preds = %loop
7479

7580
; Show that b^27 (27 = 1 + 2 + 8 + 16) is expanded correctly.
7681
define i32 @test_03(i32 %a) {
77-
; CHECK-LABEL: @test_03
78-
; CHECK: entry:
79-
; CHECK-NEXT: br label %loop
80-
; CHECK: loop:
81-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
82-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
83-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
84-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
85-
; CHECK: exit:
86-
; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
87-
; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
88-
; CHECK-NEXT: [[B3:[^ ]+]] = mul i32 [[B]], [[B2]]
89-
; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
90-
; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
91-
; CHECK-NEXT: [[B11:[^ ]+]] = mul i32 [[B3]], [[B8]]
92-
; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
93-
; CHECK-NEXT: [[B27:[^ ]+]] = mul i32 [[B11]], [[B16]]
94-
; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B27]], -1
95-
; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
96-
; CHECK-NEXT: ret i32 [[R2]]
82+
; CHECK-LABEL: define i32 @test_03(
83+
; CHECK-SAME: i32 [[A:%.*]]) {
84+
; CHECK-NEXT: [[ENTRY:.*]]:
85+
; CHECK-NEXT: br label %[[LOOP:.*]]
86+
; CHECK: [[LOOP]]:
87+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
88+
; CHECK-NEXT: [[B:%.*]] = add i32 [[A]], 1
89+
; CHECK-NEXT: [[B_POW_2:%.*]] = mul i32 [[B]], [[B]]
90+
; CHECK-NEXT: [[B_POW_4:%.*]] = mul i32 [[B_POW_2]], [[B_POW_2]]
91+
; CHECK-NEXT: [[B_POW_8:%.*]] = mul i32 [[B_POW_4]], [[B_POW_4]]
92+
; CHECK-NEXT: [[B_POW_16:%.*]] = mul i32 [[B_POW_8]], [[B_POW_8]]
93+
; CHECK-NEXT: [[B_POW_24:%.*]] = mul i32 [[B_POW_16]], [[B_POW_8]]
94+
; CHECK-NEXT: [[B_POW_25:%.*]] = mul i32 [[B_POW_24]], [[B]]
95+
; CHECK-NEXT: [[B_POW_26:%.*]] = mul i32 [[B_POW_25]], [[B]]
96+
; CHECK-NEXT: [[B_POW_27:%.*]] = mul i32 [[B_POW_26]], [[B]]
97+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
98+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
99+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
100+
; CHECK: [[EXIT]]:
101+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[B_POW_27]], -1
102+
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[LSR_IV_NEXT]]
103+
; CHECK-NEXT: ret i32 [[TMP1]]
104+
;
97105
entry:
98106
br label %loop
99107

@@ -119,23 +127,25 @@ exit: ; preds = %loop
119127

120128
; Show how linear calculation of b^16 is turned into logarithmic.
121129
define i32 @test_04(i32 %a) {
122-
; CHECK-LABEL: @test_04
123-
; CHECK: entry:
124-
; CHECK-NEXT: br label %loop
125-
; CHECK: loop:
126-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
127-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
128-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
129-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
130-
; CHECK: exit:
131-
; CHECK-NEXT: [[B:[^ ]+]] = add i32 %a, 1
132-
; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
133-
; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
134-
; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
135-
; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
136-
; CHECK-NEXT: [[R1:[^ ]+]] = add i32 [[B16]], -1
137-
; CHECK-NEXT: [[R2:[^ ]+]] = sub i32 [[R1]], [[IV_INC]]
138-
; CHECK-NEXT: ret i32 [[R2]]
130+
; CHECK-LABEL: define i32 @test_04(
131+
; CHECK-SAME: i32 [[A:%.*]]) {
132+
; CHECK-NEXT: [[ENTRY:.*]]:
133+
; CHECK-NEXT: br label %[[LOOP:.*]]
134+
; CHECK: [[LOOP]]:
135+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
136+
; CHECK-NEXT: [[B:%.*]] = add i32 [[A]], 1
137+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
138+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
139+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
140+
; CHECK: [[EXIT]]:
141+
; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[B]], [[B]]
142+
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[TMP0]]
143+
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], [[TMP1]]
144+
; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
145+
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -1
146+
; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], [[LSR_IV_NEXT]]
147+
; CHECK-NEXT: ret i32 [[TMP5]]
148+
;
139149
entry:
140150
br label %loop
141151

@@ -169,67 +179,154 @@ exit: ; preds = %loop
169179
; The output here is reasonably big, we just check that the amount of expanded
170180
; instructions is sane.
171181
define i32 @test_05(i32 %a) {
172-
; CHECK-LABEL: @test_05
173-
; CHECK: entry:
174-
; CHECK-NEXT: br label %loop
175-
; CHECK: loop:
176-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
177-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
178-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
179-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
180-
; CHECK: exit:
181-
; CHECK: %100
182-
; CHECK-NOT: %150
182+
; CHECK-LABEL: define i32 @test_05(
183+
; CHECK-SAME: i32 [[A:%.*]]) {
184+
; CHECK-NEXT: [[ENTRY:.*]]:
185+
; CHECK-NEXT: br label %[[LOOP:.*]]
186+
; CHECK: [[LOOP]]:
187+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
188+
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[A]], 1
189+
; CHECK-NEXT: [[MUL4:%.*]] = mul i32 [[ADD]], [[ADD]]
190+
; CHECK-NEXT: [[MUL5:%.*]] = mul i32 [[MUL4]], [[MUL4]]
191+
; CHECK-NEXT: [[MUL6:%.*]] = mul i32 [[MUL5]], [[MUL5]]
192+
; CHECK-NEXT: [[MUL7:%.*]] = mul i32 [[MUL6]], [[MUL6]]
193+
; CHECK-NEXT: [[MUL8:%.*]] = mul i32 [[MUL7]], [[MUL7]]
194+
; CHECK-NEXT: [[MUL9:%.*]] = mul i32 [[MUL8]], [[MUL8]]
195+
; CHECK-NEXT: [[MUL10:%.*]] = mul i32 [[MUL9]], [[MUL9]]
196+
; CHECK-NEXT: [[MUL11:%.*]] = mul i32 [[MUL10]], [[MUL10]]
197+
; CHECK-NEXT: [[MUL12:%.*]] = mul i32 [[MUL11]], [[MUL11]]
198+
; CHECK-NEXT: [[MUL13:%.*]] = mul i32 [[MUL12]], [[MUL12]]
199+
; CHECK-NEXT: [[MUL14:%.*]] = mul i32 [[MUL13]], [[MUL13]]
200+
; CHECK-NEXT: [[MUL15:%.*]] = mul i32 [[MUL14]], [[MUL14]]
201+
; CHECK-NEXT: [[MUL16:%.*]] = mul i32 [[MUL15]], [[MUL15]]
202+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
203+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
204+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
205+
; CHECK: [[EXIT]]:
206+
; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[MUL16]], [[MUL15]]
207+
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[TMP0]], [[MUL14]]
208+
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], [[MUL13]]
209+
; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[MUL12]]
210+
; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[MUL11]]
211+
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[MUL10]]
212+
; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP5]], [[MUL9]]
213+
; CHECK-NEXT: [[TMP7:%.*]] = mul i32 [[TMP6]], [[MUL8]]
214+
; CHECK-NEXT: [[TMP8:%.*]] = mul i32 [[ADD]], [[ADD]]
215+
; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP8]], [[TMP8]]
216+
; CHECK-NEXT: [[TMP10:%.*]] = mul i32 [[TMP9]], [[TMP9]]
217+
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], [[TMP10]]
218+
; CHECK-NEXT: [[TMP12:%.*]] = mul i32 [[TMP11]], [[TMP11]]
219+
; CHECK-NEXT: [[TMP13:%.*]] = mul i32 [[TMP7]], [[TMP12]]
220+
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], [[MUL16]]
221+
; CHECK-NEXT: [[TMP15:%.*]] = mul i32 [[TMP14]], [[MUL15]]
222+
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], [[MUL14]]
223+
; CHECK-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], [[MUL13]]
224+
; CHECK-NEXT: [[TMP18:%.*]] = mul i32 [[TMP17]], [[MUL12]]
225+
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], [[MUL11]]
226+
; CHECK-NEXT: [[TMP20:%.*]] = mul i32 [[TMP19]], [[MUL10]]
227+
; CHECK-NEXT: [[TMP21:%.*]] = mul i32 [[TMP20]], [[MUL9]]
228+
; CHECK-NEXT: [[TMP22:%.*]] = mul i32 [[TMP21]], [[MUL8]]
229+
; CHECK-NEXT: [[TMP23:%.*]] = mul i32 [[ADD]], [[ADD]]
230+
; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], [[TMP23]]
231+
; CHECK-NEXT: [[TMP25:%.*]] = mul i32 [[TMP24]], [[TMP24]]
232+
; CHECK-NEXT: [[TMP26:%.*]] = mul i32 [[TMP25]], [[TMP25]]
233+
; CHECK-NEXT: [[TMP27:%.*]] = mul i32 [[TMP26]], [[TMP26]]
234+
; CHECK-NEXT: [[TMP28:%.*]] = mul i32 [[TMP22]], [[TMP27]]
235+
; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[TMP13]]
236+
; CHECK-NEXT: [[TMP30:%.*]] = mul i32 [[TMP29]], [[MUL16]]
237+
; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[MUL15]]
238+
; CHECK-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[MUL14]]
239+
; CHECK-NEXT: [[TMP33:%.*]] = mul i32 [[TMP32]], [[MUL13]]
240+
; CHECK-NEXT: [[TMP34:%.*]] = mul i32 [[TMP33]], [[MUL12]]
241+
; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], [[MUL11]]
242+
; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[MUL10]]
243+
; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], [[MUL9]]
244+
; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[MUL8]]
245+
; CHECK-NEXT: [[TMP39:%.*]] = mul i32 [[ADD]], [[ADD]]
246+
; CHECK-NEXT: [[TMP40:%.*]] = mul i32 [[TMP39]], [[TMP39]]
247+
; CHECK-NEXT: [[TMP41:%.*]] = mul i32 [[TMP40]], [[TMP40]]
248+
; CHECK-NEXT: [[TMP42:%.*]] = mul i32 [[TMP41]], [[TMP41]]
249+
; CHECK-NEXT: [[TMP43:%.*]] = mul i32 [[TMP42]], [[TMP42]]
250+
; CHECK-NEXT: [[TMP44:%.*]] = mul i32 [[TMP38]], [[TMP43]]
251+
; CHECK-NEXT: [[TMP45:%.*]] = mul i32 [[TMP44]], [[TMP28]]
252+
; CHECK-NEXT: [[TMP46:%.*]] = mul i32 [[TMP45]], [[TMP13]]
253+
; CHECK-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], [[MUL16]]
254+
; CHECK-NEXT: [[TMP48:%.*]] = mul i32 [[TMP47]], [[MUL15]]
255+
; CHECK-NEXT: [[TMP49:%.*]] = mul i32 [[TMP48]], [[MUL14]]
256+
; CHECK-NEXT: [[TMP50:%.*]] = mul i32 [[TMP49]], [[MUL13]]
257+
; CHECK-NEXT: [[TMP51:%.*]] = mul i32 [[TMP50]], [[MUL12]]
258+
; CHECK-NEXT: [[TMP52:%.*]] = mul i32 [[TMP51]], [[MUL11]]
259+
; CHECK-NEXT: [[TMP53:%.*]] = mul i32 [[TMP52]], [[MUL10]]
260+
; CHECK-NEXT: [[TMP54:%.*]] = mul i32 [[TMP53]], [[MUL9]]
261+
; CHECK-NEXT: [[TMP55:%.*]] = mul i32 [[TMP54]], [[MUL8]]
262+
; CHECK-NEXT: [[TMP56:%.*]] = mul i32 [[ADD]], [[ADD]]
263+
; CHECK-NEXT: [[TMP57:%.*]] = mul i32 [[TMP56]], [[TMP56]]
264+
; CHECK-NEXT: [[TMP58:%.*]] = mul i32 [[TMP57]], [[TMP57]]
265+
; CHECK-NEXT: [[TMP59:%.*]] = mul i32 [[TMP58]], [[TMP58]]
266+
; CHECK-NEXT: [[TMP60:%.*]] = mul i32 [[TMP59]], [[TMP59]]
267+
; CHECK-NEXT: [[TMP61:%.*]] = mul i32 [[TMP55]], [[TMP60]]
268+
; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP61]], -1
269+
; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP62]], [[LSR_IV_NEXT]]
270+
; CHECK-NEXT: ret i32 [[TMP63]]
271+
;
183272

184273
entry:
185274
br label %loop
186275

187276
loop: ; preds = %loop, %entry
188277
%indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %loop ]
189-
%tmp3 = add i32 %a, 1
190-
%tmp4 = mul i32 %tmp3, %tmp3
191-
%tmp5 = mul i32 %tmp4, %tmp4
192-
%tmp6 = mul i32 %tmp5, %tmp5
193-
%tmp7 = mul i32 %tmp6, %tmp6
194-
%tmp8 = mul i32 %tmp7, %tmp7
195-
%tmp9 = mul i32 %tmp8, %tmp8
196-
%tmp10 = mul i32 %tmp9, %tmp9
197-
%tmp11 = mul i32 %tmp10, %tmp10
198-
%tmp12 = mul i32 %tmp11, %tmp11
199-
%tmp13 = mul i32 %tmp12, %tmp12
200-
%tmp14 = mul i32 %tmp13, %tmp13
201-
%tmp15 = mul i32 %tmp14, %tmp14
202-
%tmp16 = mul i32 %tmp15, %tmp15
203-
%tmp17 = mul i32 %tmp16, %tmp16
204-
%tmp18 = mul i32 %tmp17, %tmp17
205-
%tmp19 = mul i32 %tmp18, %tmp18
206-
%tmp20 = mul i32 %tmp19, %tmp19
207-
%tmp22 = add i32 %tmp20, %indvars.iv
278+
%add = add i32 %a, 1
279+
%mul4 = mul i32 %add, %add
280+
%mul5 = mul i32 %mul4, %mul4
281+
%mul6 = mul i32 %mul5, %mul5
282+
%mul7 = mul i32 %mul6, %mul6
283+
%mul8 = mul i32 %mul7, %mul7
284+
%mul9 = mul i32 %mul8, %mul8
285+
%mul10 = mul i32 %mul9, %mul9
286+
%mul11 = mul i32 %mul10, %mul10
287+
%mul12 = mul i32 %mul11, %mul11
288+
%mul13 = mul i32 %mul12, %mul12
289+
%mul14 = mul i32 %mul13, %mul13
290+
%mul15 = mul i32 %mul14, %mul14
291+
%mul16 = mul i32 %mul15, %mul15
292+
%mul17 = mul i32 %mul16, %mul16
293+
%mul18 = mul i32 %mul17, %mul17
294+
%mul19 = mul i32 %mul18, %mul18
295+
%mul20 = mul i32 %mul19, %mul19
296+
%res = add i32 %mul20, %indvars.iv
208297
%indvars.iv.next = add nuw nsw i32 %indvars.iv, 1
209298
%exitcond = icmp eq i32 %indvars.iv.next, 80
210299
br i1 %exitcond, label %exit, label %loop
211300

212301
exit: ; preds = %loop
213-
ret i32 %tmp22
302+
ret i32 %res
214303
}
215304

216305
; Show that the transformation works even if the calculation involves different
217306
; values inside.
218307
define i32 @test_06(i32 %a, i32 %c) {
219-
; CHECK-LABEL: @test_06
220-
; CHECK: entry:
221-
; CHECK-NEXT: br label %loop
222-
; CHECK: loop:
223-
; CHECK-NEXT: [[IV:[^ ]+]] = phi i32 [ [[IV_INC:[^ ]+]], %loop ], [ 0, %entry ]
224-
; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], -1
225-
; CHECK-NEXT: [[EXITCOND:[^ ]+]] = icmp eq i32 [[IV_INC]], -80
226-
; CHECK-NEXT: br i1 [[EXITCOND]], label %exit, label %loop
227-
; CHECK: exit:
228-
; CHECK: [[B:[^ ]+]] = add i32 %a, 1
229-
; CHECK-NEXT: [[B2:[^ ]+]] = mul i32 [[B]], [[B]]
230-
; CHECK-NEXT: [[B4:[^ ]+]] = mul i32 [[B2]], [[B2]]
231-
; CHECK-NEXT: [[B8:[^ ]+]] = mul i32 [[B4]], [[B4]]
232-
; CHECK-NEXT: [[B16:[^ ]+]] = mul i32 [[B8]], [[B8]]
308+
; CHECK-LABEL: define i32 @test_06(
309+
; CHECK-SAME: i32 [[A:%.*]], i32 [[C:%.*]]) {
310+
; CHECK-NEXT: [[ENTRY:.*]]:
311+
; CHECK-NEXT: br label %[[LOOP:.*]]
312+
; CHECK: [[LOOP]]:
313+
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
314+
; CHECK-NEXT: [[B:%.*]] = add i32 [[A]], 1
315+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i32 [[LSR_IV]], -1
316+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], -80
317+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[EXIT:.*]], label %[[LOOP]]
318+
; CHECK: [[EXIT]]:
319+
; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[C]], [[C]]
320+
; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[C]], [[TMP0]]
321+
; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[B]], [[B]]
322+
; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP2]]
323+
; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP3]]
324+
; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[TMP4]]
325+
; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[TMP1]], [[TMP5]]
326+
; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], -1
327+
; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[TMP7]], [[LSR_IV_NEXT]]
328+
; CHECK-NEXT: ret i32 [[TMP8]]
329+
;
233330
entry:
234331
br label %loop
235332

0 commit comments

Comments
 (0)