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9 files changed

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‎llvm/lib/Transforms/Utils/IRNormalizer.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,16 +97,16 @@ class IRNormalizer {
9797
} // namespace
9898

9999
cl::opt<bool> IRNormalizer::PreserveOrder(
100-
"norm-preserve-order", cl::Hidden,
100+
"norm-preserve-order", cl::Hidden, cl::init(false),
101101
cl::desc("Preserves original instruction order"));
102102
cl::opt<bool> IRNormalizer::RenameAll(
103-
"norm-rename-all", cl::Hidden,
103+
"norm-rename-all", cl::Hidden, cl::init(true),
104104
cl::desc("Renames all instructions (including user-named)"));
105105
cl::opt<bool> IRNormalizer::FoldPreOutputs(
106-
"norm-fold-all", cl::Hidden,
106+
"norm-fold-all", cl::Hidden, cl::init(true),
107107
cl::desc("Folds all regular instructions (including pre-outputs)"));
108108
cl::opt<bool> IRNormalizer::ReorderOperands(
109-
"norm-reorder-operands", cl::Hidden,
109+
"norm-reorder-operands", cl::Hidden, cl::init(true),
110110
cl::desc("Sorts and reorders operands in commutative instructions"));
111111

112112
/// Entry method to the IRNormalizer.

‎llvm/test/Transforms/IRNormalizer/naming-args-instr-blocks.ll‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,18 @@
1-
; RUN: opt -S -passes=normalize -norm-rename-all -norm-preserve-order < %s | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

3-
; CHECK: @foo(i32 %a0)
44
define i32 @foo(i32) {
5-
; CHECK: bb{{([0-9]{5})}}
5+
; CHECK-LABEL: define i32 @foo(
6+
; CHECK-SAME: i32 [[A0:%.*]]) {
7+
; CHECK-NEXT: [[BB17254:.*:]]
8+
; CHECK-NEXT: %"vl24903([[A0]], 2)" = add i32 [[A0]], 2
9+
; CHECK-NEXT: %"op10412(vl24903)" = add i32 6, %"vl24903([[A0]], 2)"
10+
; CHECK-NEXT: ret i32 %"op10412(vl24903)"
11+
;
612
entry:
7-
; CHECK: %"vl{{([0-9]{5})}}(%a0, 2)"
8-
%a = add i32 %0, 2
9-
10-
; CHECK: %"op{{([0-9]{5})}}(6, vl{{([0-9]{5})}}(%a0, 2))"
11-
%b = add i32 %a, 6
13+
%a = add i32 %0, 2
1214

13-
ret i32 %b
15+
%b = add i32 %a, 6
16+
17+
ret i32 %b
1418
}

‎llvm/test/Transforms/IRNormalizer/naming-arguments.ll‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,13 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

3-
; CHECK: @foo(i32 %a0, i32 %a1)
44
define i32 @foo(i32, i32) {
5+
; CHECK-LABEL: define i32 @foo(
6+
; CHECK-SAME: i32 [[A0:%.*]], i32 [[A1:%.*]]) {
7+
; CHECK-NEXT: [[BB17254:.*:]]
8+
; CHECK-NEXT: %"vl20416([[A0]], [[A1]])" = mul i32 [[A0]], [[A1]]
9+
; CHECK-NEXT: ret i32 %"vl20416([[A0]], [[A1]])"
10+
;
511
%tmp = mul i32 %0, %1
612
ret i32 %tmp
713
}

‎llvm/test/Transforms/IRNormalizer/naming.ll‎

Lines changed: 16 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,30 @@
1-
; RUN: opt -S -passes=normalize -norm-rename-all < %s | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

34
define i32 @foo(i32 %a0) {
4-
; CHECK: bb{{([0-9]{5})}}
5+
; CHECK-LABEL: define i32 @foo(
6+
; CHECK-SAME: i32 [[A0:%.*]]) {
7+
; CHECK-NEXT: [[BB17254:.*:]]
8+
; CHECK-NEXT: %"vl12603([[A0]], 2)" = add i32 [[A0]], 2
9+
; CHECK-NEXT: ret i32 %"vl12603([[A0]], 2)"
10+
;
511
entry:
612
%a = add i32 %a0, 2
713
ret i32 %a
814
}
915

1016
define i32 @bar(i32 %a0) {
17+
; CHECK-LABEL: define i32 @bar(
18+
; CHECK-SAME: i32 [[A0:%.*]]) {
19+
; CHECK-NEXT: [[BB17254:.*:]]
20+
; CHECK-NEXT: %"vl76167([[A0]], 2)" = add i32 [[A0]], 2
21+
; CHECK-NEXT: %"op10412(vl76167)" = add i32 6, %"vl76167([[A0]], 2)"
22+
; CHECK-NEXT: %"op10412(op10412)" = add i32 8, %"op10412(vl76167)"
23+
; CHECK-NEXT: ret i32 %"op10412(op10412)"
24+
;
1125
entry:
12-
; CHECK: %"vl{{([0-9]{5})}}(%a0, 2)"
1326
%a = add i32 %a0, 2
14-
; CHECK: %"op{{([0-9]{5})}}(vl{{([0-9]{5})}})"
1527
%b = add i32 %a, 6
16-
; CHECK: %"op{{([0-9]{5})}}(8, op{{([0-9]{5})}}(6, vl{{([0-9]{5})}}(%a0, 2)))"
1728
%c = add i32 %b, 8
1829
ret i32 %c
1930
}

‎llvm/test/Transforms/IRNormalizer/regression-coro-elide-musttail.ll‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,14 @@
1-
; RUN: opt < %s -passes=normalize -verify-each
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

34
define fastcc void @foo.resume_musttail(ptr %FramePtr) {
5+
; CHECK-LABEL: define fastcc void @foo.resume_musttail(
6+
; CHECK-SAME: ptr [[A0:%.*]]) {
7+
; CHECK-NEXT: [[BB15160:.*:]]
8+
; CHECK-NEXT: [[TMP0:%.*]] = tail call token @llvm.coro.id(i32 0, ptr null, ptr null, ptr null)
9+
; CHECK-NEXT: musttail call fastcc void undef(ptr null)
10+
; CHECK-NEXT: ret void
11+
;
412
entry:
513
%0 = tail call token @llvm.coro.id(i32 0, ptr null, ptr null, ptr null)
614
musttail call fastcc void undef(ptr null)

‎llvm/test/Transforms/IRNormalizer/regression-deoptimize.ll‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
1-
; RUN: opt < %s -passes=normalize -verify-each
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

34
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
45

‎llvm/test/Transforms/IRNormalizer/regression-dont-hoist-deoptimize.ll‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,18 @@
1-
; RUN: opt %s -passes=normalize -verify-each
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
3+
24
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
35
target triple = "x86_64-unknown-linux-gnu"
46

57
declare void @llvm.experimental.deoptimize.isVoid(...)
68

79
define void @widget() {
10+
; CHECK-LABEL: define void @widget() {
11+
; CHECK-NEXT: [[BB15160:.*:]]
12+
; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 0 to i32
13+
; CHECK-NEXT: call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]
14+
; CHECK-NEXT: ret void
15+
;
816
bb:
917
%tmp3 = trunc i64 0 to i32
1018
call void (...) @llvm.experimental.deoptimize.isVoid(i32 0) [ "deopt"() ]

‎llvm/test/Transforms/IRNormalizer/regression-infinite-loop.ll‎

Lines changed: 98 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,103 @@
1-
; RUN: opt -passes=normalize -norm-preserve-order=true < %s
2-
; RUN: opt -passes=normalize -norm-preserve-order=false < %s
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -S -passes=normalize < %s | FileCheck %s
33

44
define void @test(ptr, i32) {
5+
; CHECK-LABEL: define void @test(
6+
; CHECK-SAME: ptr [[A0:%.*]], i32 [[A1:%.*]]) {
7+
; CHECK-NEXT: [[BB76951:.*]]:
8+
; CHECK-NEXT: %"vl72693([[A1]], 1)" = add i32 [[A1]], 1
9+
; CHECK-NEXT: br label %[[BB16110:.*]]
10+
; CHECK: [[BB16110]]:
11+
; CHECK-NEXT: %"op10912(op18080, vl72693)" = phi i32 [ %"op18080(op10412, op17645)", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
12+
; CHECK-NEXT: %"op10912(op17645, vl72693)" = phi i32 [ %"op17645(op10912)70", %[[BB16110]] ], [ %"vl72693([[A1]], 1)", %[[BB76951]] ]
13+
; CHECK-NEXT: %"op15084(op10912)" = mul i32 %"op10912(op18080, vl72693)", undef
14+
; CHECK-NEXT: %"op16562(op15084)" = xor i32 -1, %"op15084(op10912)"
15+
; CHECK-NEXT: %"op44627(op10912, op16562)" = add i32 %"op10912(op18080, vl72693)", %"op16562(op15084)"
16+
; CHECK-NEXT: %"op17645(op10912)" = add i32 -1, %"op10912(op17645, vl72693)"
17+
; CHECK-NEXT: %"op18080(op17645, op44627)" = add i32 %"op17645(op10912)", %"op44627(op10912, op16562)"
18+
; CHECK-NEXT: %"op17720(op15084, op18080)" = mul i32 %"op15084(op10912)", %"op18080(op17645, op44627)"
19+
; CHECK-NEXT: %"op16562(op17720)" = xor i32 -1, %"op17720(op15084, op18080)"
20+
; CHECK-NEXT: %"op17430(op16562, op18080)" = add i32 %"op16562(op17720)", %"op18080(op17645, op44627)"
21+
; CHECK-NEXT: %"op10412(op17430)" = add i32 %"op17430(op16562, op18080)", undef
22+
; CHECK-NEXT: %"op17720(op10412, op17720)" = mul i32 %"op10412(op17430)", %"op17720(op15084, op18080)"
23+
; CHECK-NEXT: %"op16562(op17720)1" = xor i32 -1, %"op17720(op10412, op17720)"
24+
; CHECK-NEXT: %"op17430(op10412, op16562)" = add i32 %"op10412(op17430)", %"op16562(op17720)1"
25+
; CHECK-NEXT: %"op10412(op17430)2" = add i32 %"op17430(op10412, op16562)", undef
26+
; CHECK-NEXT: %"op10412(op10412)" = add i32 %"op10412(op17430)2", undef
27+
; CHECK-NEXT: %"op10412(op10412)3" = add i32 %"op10412(op10412)", undef
28+
; CHECK-NEXT: %"op17720(op10412, op17720)4" = mul i32 %"op10412(op17430)2", %"op17720(op10412, op17720)"
29+
; CHECK-NEXT: %"op17720(op10412, op17720)5" = mul i32 %"op10412(op10412)3", %"op17720(op10412, op17720)4"
30+
; CHECK-NEXT: %"op16562(op17720)6" = xor i32 -1, %"op17720(op10412, op17720)5"
31+
; CHECK-NEXT: %"op17430(op10412, op16562)7" = add i32 %"op10412(op10412)3", %"op16562(op17720)6"
32+
; CHECK-NEXT: %"op10412(op17430)8" = add i32 %"op17430(op10412, op16562)7", undef
33+
; CHECK-NEXT: %"op17720(op10412, op17720)9" = mul i32 %"op10412(op17430)8", %"op17720(op10412, op17720)5"
34+
; CHECK-NEXT: %"op16562(op17720)10" = xor i32 -1, %"op17720(op10412, op17720)9"
35+
; CHECK-NEXT: %"op17430(op10412, op16562)11" = add i32 %"op10412(op17430)8", %"op16562(op17720)10"
36+
; CHECK-NEXT: %"op10412(op17430)12" = add i32 %"op17430(op10412, op16562)11", undef
37+
; CHECK-NEXT: %"op17720(op10412, op17720)13" = mul i32 %"op10412(op17430)12", %"op17720(op10412, op17720)9"
38+
; CHECK-NEXT: %"op16562(op17720)14" = xor i32 -1, %"op17720(op10412, op17720)13"
39+
; CHECK-NEXT: %"op17430(op10412, op16562)15" = add i32 %"op10412(op17430)12", %"op16562(op17720)14"
40+
; CHECK-NEXT: %"op10412(op17430)16" = add i32 %"op17430(op10412, op16562)15", undef
41+
; CHECK-NEXT: %"op17720(op10412, op17720)17" = mul i32 %"op10412(op17430)16", %"op17720(op10412, op17720)13"
42+
; CHECK-NEXT: %"op16562(op17720)18" = xor i32 -1, %"op17720(op10412, op17720)17"
43+
; CHECK-NEXT: %"op17430(op10412, op16562)19" = add i32 %"op10412(op17430)16", %"op16562(op17720)18"
44+
; CHECK-NEXT: %"op10412(op17430)20" = add i32 %"op17430(op10412, op16562)19", undef
45+
; CHECK-NEXT: %"op17720(op10412, op17720)21" = mul i32 %"op10412(op17430)20", %"op17720(op10412, op17720)17"
46+
; CHECK-NEXT: %"op16562(op17720)22" = xor i32 -1, %"op17720(op10412, op17720)21"
47+
; CHECK-NEXT: %"op17430(op10412, op16562)23" = add i32 %"op10412(op17430)20", %"op16562(op17720)22"
48+
; CHECK-NEXT: %"op17645(op10912)24" = add i32 -9, %"op10912(op17645, vl72693)"
49+
; CHECK-NEXT: %"op18080(op17430, op17645)" = add i32 %"op17430(op10412, op16562)23", %"op17645(op10912)24"
50+
; CHECK-NEXT: %"op17720(op17720, op18080)" = mul i32 %"op17720(op10412, op17720)21", %"op18080(op17430, op17645)"
51+
; CHECK-NEXT: %"op16562(op17720)25" = xor i32 -1, %"op17720(op17720, op18080)"
52+
; CHECK-NEXT: %"op17430(op16562, op18080)26" = add i32 %"op16562(op17720)25", %"op18080(op17430, op17645)"
53+
; CHECK-NEXT: %"op10412(op17430)27" = add i32 %"op17430(op16562, op18080)26", undef
54+
; CHECK-NEXT: %"op17720(op10412, op17720)28" = mul i32 %"op10412(op17430)27", %"op17720(op17720, op18080)"
55+
; CHECK-NEXT: %"op16562(op17720)29" = xor i32 -1, %"op17720(op10412, op17720)28"
56+
; CHECK-NEXT: %"op17430(op10412, op16562)30" = add i32 %"op10412(op17430)27", %"op16562(op17720)29"
57+
; CHECK-NEXT: %"op10412(op17430)31" = add i32 %"op17430(op10412, op16562)30", undef
58+
; CHECK-NEXT: %"op17720(op10412, op17720)32" = mul i32 %"op10412(op17430)31", %"op17720(op10412, op17720)28"
59+
; CHECK-NEXT: %"op16562(op17720)33" = xor i32 -1, %"op17720(op10412, op17720)32"
60+
; CHECK-NEXT: %"op17430(op10412, op16562)34" = add i32 %"op10412(op17430)31", %"op16562(op17720)33"
61+
; CHECK-NEXT: %"op10412(op17430)35" = add i32 %"op17430(op10412, op16562)34", undef
62+
; CHECK-NEXT: %"op17720(op10412, op17720)36" = mul i32 %"op10412(op17430)35", %"op17720(op10412, op17720)32"
63+
; CHECK-NEXT: %"op16562(op17720)37" = xor i32 -1, %"op17720(op10412, op17720)36"
64+
; CHECK-NEXT: %"op17430(op10412, op16562)38" = add i32 %"op10412(op17430)35", %"op16562(op17720)37"
65+
; CHECK-NEXT: %"op10412(op17430)39" = add i32 %"op17430(op10412, op16562)38", undef
66+
; CHECK-NEXT: %"op17720(op10412, op17720)40" = mul i32 %"op10412(op17430)39", %"op17720(op10412, op17720)36"
67+
; CHECK-NEXT: %"op16562(op17720)41" = xor i32 -1, %"op17720(op10412, op17720)40"
68+
; CHECK-NEXT: %"op17430(op10412, op16562)42" = add i32 %"op10412(op17430)39", %"op16562(op17720)41"
69+
; CHECK-NEXT: %"op17645(op10912)43" = add i32 -14, %"op10912(op17645, vl72693)"
70+
; CHECK-NEXT: %"op18080(op17430, op17645)44" = add i32 %"op17430(op10412, op16562)42", %"op17645(op10912)43"
71+
; CHECK-NEXT: %"op17720(op17720, op18080)45" = mul i32 %"op17720(op10412, op17720)40", %"op18080(op17430, op17645)44"
72+
; CHECK-NEXT: %"op16562(op17720)46" = xor i32 -1, %"op17720(op17720, op18080)45"
73+
; CHECK-NEXT: %"op17430(op16562, op18080)47" = add i32 %"op16562(op17720)46", %"op18080(op17430, op17645)44"
74+
; CHECK-NEXT: %"op10412(op17430)48" = add i32 %"op17430(op16562, op18080)47", undef
75+
; CHECK-NEXT: %"op17720(op10412, op17720)49" = mul i32 %"op10412(op17430)48", %"op17720(op17720, op18080)45"
76+
; CHECK-NEXT: %"op16562(op17720)50" = xor i32 -1, %"op17720(op10412, op17720)49"
77+
; CHECK-NEXT: %"op17430(op10412, op16562)51" = add i32 %"op10412(op17430)48", %"op16562(op17720)50"
78+
; CHECK-NEXT: %"op10412(op17430)52" = add i32 %"op17430(op10412, op16562)51", undef
79+
; CHECK-NEXT: %"op17720(op10412, op17720)53" = mul i32 %"op10412(op17430)52", %"op17720(op10412, op17720)49"
80+
; CHECK-NEXT: %"op16562(op17720)54" = xor i32 -1, %"op17720(op10412, op17720)53"
81+
; CHECK-NEXT: %"op17430(op10412, op16562)55" = add i32 %"op10412(op17430)52", %"op16562(op17720)54"
82+
; CHECK-NEXT: %"op10412(op17430)56" = add i32 %"op17430(op10412, op16562)55", undef
83+
; CHECK-NEXT: %"op17720(op10412, op17720)57" = mul i32 %"op10412(op17430)56", %"op17720(op10412, op17720)53"
84+
; CHECK-NEXT: %"op16562(op17720)58" = xor i32 -1, %"op17720(op10412, op17720)57"
85+
; CHECK-NEXT: %"op17430(op10412, op16562)59" = add i32 %"op10412(op17430)56", %"op16562(op17720)58"
86+
; CHECK-NEXT: %"op10412(op17430)60" = add i32 %"op17430(op10412, op16562)59", undef
87+
; CHECK-NEXT: %"op17720(op10412, op17720)61" = mul i32 %"op10412(op17430)60", %"op17720(op10412, op17720)57"
88+
; CHECK-NEXT: %"op16562(op17720)62" = xor i32 -1, %"op17720(op10412, op17720)61"
89+
; CHECK-NEXT: %"op17430(op10412, op16562)63" = add i32 %"op10412(op17430)60", %"op16562(op17720)62"
90+
; CHECK-NEXT: %"op10412(op17430)64" = add i32 %"op17430(op10412, op16562)63", undef
91+
; CHECK-NEXT: %"op17720(op10412, op17720)65" = mul i32 %"op10412(op17430)64", %"op17720(op10412, op17720)61"
92+
; CHECK-NEXT: %"op16562(op17720)66" = xor i32 -1, %"op17720(op10412, op17720)65"
93+
; CHECK-NEXT: %"op17430(op10412, op16562)67" = add i32 %"op10412(op17430)64", %"op16562(op17720)66"
94+
; CHECK-NEXT: %"op10412(op17430)68" = add i32 %"op17430(op10412, op16562)67", undef
95+
; CHECK-NEXT: %"op10412(op10412)69" = add i32 %"op10412(op17430)68", undef
96+
; CHECK-NEXT: %"op17645(op10912)70" = add i32 -21, %"op10912(op17645, vl72693)"
97+
; CHECK-NEXT: %"op18080(op10412, op17645)" = add i32 %"op10412(op10412)69", %"op17645(op10912)70"
98+
; CHECK-NEXT: store i32 %"op18080(op10412, op17645)", ptr [[A0]], align 4
99+
; CHECK-NEXT: br label %[[BB16110]]
100+
;
5101
bb:
6102
%a = add i32 %1, 1
7103
br label %bb1

‎llvm/test/Transforms/IRNormalizer/reordering-basic.ll‎

Lines changed: 25 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,17 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt -S -passes=normalize < %s | FileCheck %s
23

34
define double @foo(double %a0, double %a1) {
4-
; CHECK-LABEL: foo(
5+
; CHECK-LABEL: define double @foo(
6+
; CHECK-SAME: double [[A0:%.*]], double [[A1:%.*]]) {
7+
; CHECK-NEXT: [[BB17254:.*:]]
8+
; CHECK-NEXT: %"vl93562([[A0]], 2.000000e+00)" = fmul double [[A0]], 2.000000e+00
9+
; CHECK-NEXT: %"op95858(vl93562)" = fmul double 6.000000e+00, %"vl93562([[A0]], 2.000000e+00)"
10+
; CHECK-NEXT: [[A:%.*]] = fmul double [[A0]], [[A1]]
11+
; CHECK-NEXT: [[C:%.*]] = fmul double 6.000000e+00, [[A]]
12+
; CHECK-NEXT: ret double %"op95858(vl93562)"
13+
;
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entry:
6-
; CHECK: %b
7-
; CHECK: %d
8-
; CHECK: %a
9-
; CHECK: %c
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%a = fmul double %a0, %a1
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%b = fmul double %a0, 2.000000e+00
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%c = fmul double %a, 6.000000e+00
@@ -19,7 +24,21 @@ declare double @bir()
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declare double @bar()
2025

2126
define double @baz(double %x) {
22-
; CHECK-LABEL: baz(
27+
; CHECK-LABEL: define double @baz(
28+
; CHECK-SAME: double [[A0:%.*]]) {
29+
; CHECK-NEXT: [[BB76951:.*:]]
30+
; CHECK-NEXT: [[IFCOND:%.*]] = fcmp one double [[A0]], 0.000000e+00
31+
; CHECK-NEXT: br i1 [[IFCOND]], label %[[BB91455:.*]], label %[[BB914551:.*]]
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; CHECK: [[BB91455]]:
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; CHECK-NEXT: %"vl15001bir()" = call double @bir()
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; CHECK-NEXT: br label %[[BB17254:.*]]
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; CHECK: [[BB914551]]:
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; CHECK-NEXT: %"vl69719bar()" = call double @bar()
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; CHECK-NEXT: br label %[[BB17254]]
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; CHECK: [[BB17254]]:
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; CHECK-NEXT: %"op19734(vl15001, vl69719)" = phi double [ %"vl15001bir()", %[[BB91455]] ], [ %"vl69719bar()", %[[BB914551]] ]
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; CHECK-NEXT: ret double %"op19734(vl15001, vl69719)"
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;
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entry:
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%ifcond = fcmp one double %x, 0.000000e+00
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br i1 %ifcond, label %then, label %else
@@ -33,7 +52,6 @@ else: ; preds = %entry
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br label %ifcont
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ifcont: ; preds = %else, %then
36-
; CHECK: %iftmp = phi double [ %calltmp1, %else ], [ %calltmp, %then ]
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%iftmp = phi double [ %calltmp, %then ], [ %calltmp1, %else ]
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ret double %iftmp
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}

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