@@ -696,16 +696,14 @@ def Zn4WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]>
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def : InstRW<[Zn4WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
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// Integer division.
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- // FIXME: uops for 8-bit division measures as 2. for others it's a guess.
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- // FIXME: latency for 8-bit division measures as 10. for others it's a guess.
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- defm : Zn4WriteResIntPair<WriteDiv8, [Zn4Divider], 10, [10], 2>;
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- defm : Zn4WriteResIntPair<WriteDiv16, [Zn4Divider], 11, [11], 2>;
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- defm : Zn4WriteResIntPair<WriteDiv32, [Zn4Divider], 13, [13], 2>;
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- defm : Zn4WriteResIntPair<WriteDiv64, [Zn4Divider], 17, [17], 2>;
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- defm : Zn4WriteResIntPair<WriteIDiv8, [Zn4Divider], 10, [10], 2>;
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- defm : Zn4WriteResIntPair<WriteIDiv16, [Zn4Divider], 11, [11], 2>;
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- defm : Zn4WriteResIntPair<WriteIDiv32, [Zn4Divider], 13, [13], 2>;
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- defm : Zn4WriteResIntPair<WriteIDiv64, [Zn4Divider], 17, [17], 2>;
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+ defm : Zn4WriteResIntPair<WriteDiv8, [Zn4Divider], 9, [9], 2>;
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+ defm : Zn4WriteResIntPair<WriteDiv16, [Zn4Divider], 10, [10], 2>;
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+ defm : Zn4WriteResIntPair<WriteDiv32, [Zn4Divider], 12, [12], 2>;
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+ defm : Zn4WriteResIntPair<WriteDiv64, [Zn4Divider], 18, [18], 2>;
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+ defm : Zn4WriteResIntPair<WriteIDiv8, [Zn4Divider], 9, [9], 2>;
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+ defm : Zn4WriteResIntPair<WriteIDiv16, [Zn4Divider], 10, [10], 2>;
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+ defm : Zn4WriteResIntPair<WriteIDiv32, [Zn4Divider], 12, [12], 2>;
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+ defm : Zn4WriteResIntPair<WriteIDiv64, [Zn4Divider], 18, [18], 2>;
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defm : Zn4WriteResIntPair<WriteBSF, [Zn4ALU1], 1, [1], 6, /*LoadUOps=*/1>; // Bit scan forward.
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defm : Zn4WriteResIntPair<WriteBSR, [Zn4ALU1], 1, [1], 6, /*LoadUOps=*/1>; // Bit scan reverse.
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