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--Added support for the extension SPV_INTEL_blocking_pipes
--Added test files for the extension SPV_INTEL_blocking_pipes
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‎llvm/docs/SPIRVUsage.rst‎

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@@ -241,6 +241,8 @@ Below is a list of supported SPIR-V extensions, sorted alphabetically by their e
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- Adds predicated load and store instructions that conditionally read from or write to memory based on a boolean predicate.
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* - ``SPV_KHR_maximal_reconvergence``
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- Adds execution mode and capability to enable maximal reconvergence.
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* - ``SPV_INTEL_blocking_pipes``
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- Adds new pipe read and write functions that have blocking semantics instead of the non-blocking semantics of the existing pipe read/write functions.
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SPIR-V representation in LLVM IR
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================================

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp‎

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@@ -2390,6 +2390,15 @@ static bool generateBindlessImageINTELInst(const SPIRV::IncomingCall *Call,
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return buildBindlessImageINTELInst(Call, Opcode, MIRBuilder, GR);
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}
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static bool generateBlockingPipesInst(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
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SPIRVGlobalRegistry *GR) {
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const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
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unsigned Opcode =
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SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode;
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return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
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}
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static bool
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generateTernaryBitwiseFunctionINTELInst(const SPIRV::IncomingCall *Call,
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MachineIRBuilder &MIRBuilder,
@@ -3050,6 +3059,8 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
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return generatePipeInst(Call.get(), MIRBuilder, GR);
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case SPIRV::PredicatedLoadStore:
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return generatePredicatedLoadStoreInst(Call.get(), MIRBuilder, GR);
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case SPIRV::BlockingPipes:
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return generateBlockingPipesInst(Call.get(), MIRBuilder, GR);
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}
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return false;
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}

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

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@@ -71,6 +71,7 @@ def TernaryBitwiseINTEL : BuiltinGroup;
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def Block2DLoadStore : BuiltinGroup;
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def Pipe : BuiltinGroup;
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def PredicatedLoadStore : BuiltinGroup;
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def BlockingPipes : BuiltinGroup;
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//===----------------------------------------------------------------------===//
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// Class defining a demangled builtin record. The information in the record
@@ -1174,6 +1175,10 @@ defm : DemangledNativeBuiltin<"clock_read_sub_group", OpenCL_std, KernelClock, 0
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defm : DemangledNativeBuiltin<"clock_read_hilo_device", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
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defm : DemangledNativeBuiltin<"clock_read_hilo_work_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
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defm : DemangledNativeBuiltin<"clock_read_hilo_sub_group", OpenCL_std, KernelClock, 0, 0, OpReadClockKHR>;
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//SPV_INTEL_blocking_pipes
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defm : DemangledNativeBuiltin<"__spirv_WritePipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpWritePipeBlockingINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_ReadPipeBlockingINTEL", OpenCL_std, BlockingPipes, 0, 0, OpReadPipeBlockingINTEL>;
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defm : DemangledNativeBuiltin<"__spirv_ReadClockKHR", OpenCL_std, KernelClock, 1, 1, OpReadClockKHR>;
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp‎

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@@ -159,7 +159,9 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
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{"SPV_KHR_maximal_reconvergence",
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SPIRV::Extension::Extension::SPV_KHR_maximal_reconvergence},
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{"SPV_INTEL_kernel_attributes",
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SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes}};
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SPIRV::Extension::Extension::SPV_INTEL_kernel_attributes},
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{"SPV_INTEL_blocking_pipes",
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SPIRV::Extension::Extension::SPV_INTEL_blocking_pipes}};
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bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
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StringRef ArgValue,

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td‎

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@@ -993,3 +993,9 @@ def OpPredicatedLoadINTEL: Op<6528, (outs ID:$res), (ins TYPE:$resType, ID:$ptr,
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"$res = OpPredicatedLoadINTEL $resType $ptr $predicate $default_value">;
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def OpPredicatedStoreINTEL: Op<6529, (outs), (ins ID:$ptr, ID:$object, ID:$predicate, variable_ops),
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"OpPredicatedStoreINTEL $ptr $object $predicate">;
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//SPV_INTEL_blocking_pipes
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def OpReadPipeBlockingINTEL :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
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"OpReadPipeBlockingINTEL $pipe $pointer $packetSize $packetAlignment">;
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def OpWritePipeBlockingINTEL :Op<5946, (outs), (ins ID:$pipe, ID:$pointer, ID:$packetSize, ID:$packetAlignment),
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"OpWritePipeBlockingINTEL $pipe $pointer $packetSize $packetAlignment">;

‎llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp‎

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@@ -1885,6 +1885,13 @@ void addInstrRequirements(const MachineInstr &MI,
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Reqs.addCapability(
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SPIRV::Capability::CooperativeMatrixCheckedInstructionsINTEL);
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break;
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case SPIRV::OpReadPipeBlockingINTEL:
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case SPIRV::OpWritePipeBlockingINTEL:
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if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_blocking_pipes)) {
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Reqs.addExtension(SPIRV::Extension::SPV_INTEL_blocking_pipes);
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Reqs.addCapability(SPIRV::Capability::BlockingPipesINTEL);
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}
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break;
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case SPIRV::OpCooperativeMatrixGetElementCoordINTEL:
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if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_joint_matrix))
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report_fatal_error("OpCooperativeMatrixGetElementCoordINTEL requires the "

‎llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td‎

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@@ -611,6 +611,7 @@ defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tenso
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defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>;
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defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>;
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defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>;
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defm BlockingPipesINTEL : CapabilityOperand<5945, 0, 0, [SPV_INTEL_blocking_pipes], []>;
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//===----------------------------------------------------------------------===//
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// Multiclass used to define SourceLanguage enum values and at the same time

‎llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_blocking_pipes/PipeBlocking.ll‎

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@@ -0,0 +1,115 @@
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_blocking_pipes %s -o - | FileCheck %s --check-prefixes=CHECK-SPIRV
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; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_blocking_pipes %s -o - -filetype=obj | spirv-val %}
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%opencl.pipe_ro_t = type opaque
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%opencl.pipe_wo_t = type opaque
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; CHECK-SPIRV: OpCapability BlockingPipesINTEL
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; CHECK-SPIRV: OpExtension "SPV_INTEL_blocking_pipes"
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; CHECK-SPIRV: %[[PipeRTy:[0-9]+]] = OpTypePipe ReadOnly
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; CHECK-SPIRV: %[[PipeWTy:[0-9]+]] = OpTypePipe WriteOnly
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; CHECK-SPIRV: %[[PipeR1:[0-9]+]] = OpLoad %[[PipeRTy]] %[[#]] Aligned 8
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; CHECK-SPIRV: OpReadPipeBlockingINTEL %[[PipeR1]] %[[#]] %[[#]] %[[#]]
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; CHECK-SPIRV: %[[PipeR2:[0-9]+]] = OpLoad %[[PipeRTy]] %[[#]] Aligned 8
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; CHECK-SPIRV: OpReadPipeBlockingINTEL %[[PipeR2]] %[[#]] %[[#]] %[[#]]
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; CHECK-SPIRV: %[[PipeW1:[0-9]+]] = OpLoad %[[PipeWTy]] %[[#]] Aligned 8
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; CHECK-SPIRV: OpWritePipeBlockingINTEL %[[PipeW1]] %[[#]] %[[#]] %[[#]]
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; CHECK-SPIRV: %[[PipeW2:[0-9]+]] = OpLoad %[[PipeWTy]] %[[#]] Aligned 8
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; CHECK-SPIRV: OpWritePipeBlockingINTEL %[[PipeW2]] %[[#]] %[[#]] %[[#]]
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func void @foo(target("spirv.Pipe", 0) %p, ptr addrspace(1) %ptr) #0 {
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entry:
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%p.addr = alloca target("spirv.Pipe", 0), align 8
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%ptr.addr = alloca ptr addrspace(1), align 8
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store target("spirv.Pipe", 0) %p, target("spirv.Pipe", 0)* %p.addr, align 8
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store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
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%0 = load target("spirv.Pipe", 0), target("spirv.Pipe", 0)* %p.addr, align 8
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%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
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%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
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call spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePiii(target("spirv.Pipe", 0) %0, ptr addrspace(4) %2, i32 4, i32 4)
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ret void
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}
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declare dso_local spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePiii(target("spirv.Pipe", 0), ptr addrspace(4), i32, i32)
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func void @bar(target("spirv.Pipe", 0) %p, ptr addrspace(1) %ptr) #0 {
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entry:
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%p.addr = alloca target("spirv.Pipe", 0), align 8
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%ptr.addr = alloca ptr addrspace(1), align 8
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store target("spirv.Pipe", 0) %p, target("spirv.Pipe", 0)* %p.addr, align 8
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store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
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%0 = load target("spirv.Pipe", 0), target("spirv.Pipe", 0)* %p.addr, align 8
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%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
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%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
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call spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePvii(target("spirv.Pipe", 0) %0, ptr addrspace(4) %2, i32 4, i32 4)
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ret void
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}
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declare dso_local spir_func void @_Z29__spirv_ReadPipeBlockingINTELIiEv8ocl_pipePvii(target("spirv.Pipe", 0), ptr addrspace(4), i32, i32)
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func void @boo(target("spirv.Pipe", 1) %p, ptr addrspace(1) %ptr) #0 {
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entry:
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%p.addr = alloca target("spirv.Pipe", 1), align 8
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%ptr.addr = alloca ptr addrspace(1), align 8
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store target("spirv.Pipe", 1) %p, target("spirv.Pipe", 1)* %p.addr, align 8
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store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
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%0 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1)* %p.addr, align 8
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%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
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%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
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call spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePiii(target("spirv.Pipe", 1) %0, ptr addrspace(4) %2, i32 4, i32 4)
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ret void
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}
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declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePiii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func void @baz(target("spirv.Pipe", 1) %p, ptr addrspace(1) %ptr) #0 {
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entry:
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%p.addr = alloca target("spirv.Pipe", 1), align 8
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%ptr.addr = alloca ptr addrspace(1), align 8
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store target("spirv.Pipe", 1) %p, target("spirv.Pipe", 1)* %p.addr, align 8
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store ptr addrspace(1) %ptr, ptr %ptr.addr, align 8
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%0 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1)* %p.addr, align 8
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%1 = load ptr addrspace(1), ptr %ptr.addr, align 8
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%2 = addrspacecast ptr addrspace(1) %1 to ptr addrspace(4)
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call spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePvii(target("spirv.Pipe", 1) %0, ptr addrspace(4) %2, i32 4, i32 4)
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ret void
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}
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declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIKiEv8ocl_pipePvii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
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; CHECK-LLVM: declare spir_func void @__read_pipe_2_bl(ptr addrspace(1), ptr addrspace(4), i32, i32)
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; CHECK-LLVM: declare spir_func void @__write_pipe_2_bl(ptr addrspace(1), ptr addrspace(4), i32, i32)
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; Function Attrs: convergent mustprogress norecurse nounwind
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define linkonce_odr dso_local spir_func void @WritePipeBLockingi9Pointer(ptr addrspace(4) align 2 dereferenceable(2) %_Data) {
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entry:
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%_Data.addr = alloca ptr addrspace(4), align 8
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%_WPipe = alloca target("spirv.Pipe", 1), align 8
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%_Data.addr.ascast = addrspacecast ptr %_Data.addr to ptr addrspace(4)
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%_WPipe.ascast = addrspacecast target("spirv.Pipe", 1)* %_WPipe to target("spirv.Pipe", 1) addrspace(4)*
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store ptr addrspace(4) %_Data, ptr addrspace(4) %_Data.addr.ascast, align 8
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%0 = bitcast target("spirv.Pipe", 1)* %_WPipe to ptr
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%1 = load target("spirv.Pipe", 1), target("spirv.Pipe", 1) addrspace(4)* %_WPipe.ascast, align 8
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%2 = load ptr addrspace(4), ptr addrspace(4) %_Data.addr.ascast, align 8
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call spir_func void @_Z30__spirv_WritePipeBlockingINTELIDU9_Ev8ocl_pipePKT_ii(target("spirv.Pipe", 1) %1, ptr addrspace(4) %2, i32 2, i32 2)
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ret void
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}
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declare dso_local spir_func void @_Z30__spirv_WritePipeBlockingINTELIDU9_Ev8ocl_pipePKT_ii(target("spirv.Pipe", 1), ptr addrspace(4), i32, i32)
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attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0}
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!opencl.ocl.version = !{!1}
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!opencl.spir.version = !{!1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 2, i32 0}
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!2 = !{!"clang version 9.0.0 (https://github.com/MrSidims/llvm.git c627b787284c5bcc917ea9742908baa1b856e176)"}
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