Addressed the reviewed changes.

Author: vg0204

llvm/include/llvm/CodeGen/LiveRegUnits.h

@@ -90,7 +90,7 @@ class LiveRegUnits {
 
   /// Adds register units covered by physical register \p Reg that are
   /// part of the lanemask \p Mask.
-  void addRegMasked(MCRegister Reg, LaneBitmask Mask) {
+  void addRegMasked(MCRegister Reg, LaneBitmask Mask = LaneBitmask::getAll()) {
     for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
       LaneBitmask UnitMask = (*Unit).second;
       if ((UnitMask & Mask).any())

llvm/include/llvm/CodeGen/MachineBasicBlock.h

@@ -13,7 +13,6 @@
 #ifndef LLVM_CODEGEN_MACHINEBASICBLOCK_H
 #define LLVM_CODEGEN_MACHINEBASICBLOCK_H
 
-#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMapInfo.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/GraphTraits.h"

llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

@@ -67,9 +67,9 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
   for (const MachineBasicBlock *Succ : BB->successors())
     for (const auto &LI : Succ->liveins()) {
       for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
-        unsigned Reg = (*AI).id();
-        Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
-        KillIndices[Reg] = BBSize;
+        MCRegister Reg = *AI;
+        Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1);
+        KillIndices[Reg.id()] = BBSize;
         DefIndices[Reg] = ~0u;
       }
     }

llvm/lib/CodeGen/LiveRegUnits.cpp

@@ -88,7 +88,7 @@ void LiveRegUnits::accumulate(const MachineInstr &MI) {
 static void addBlockLiveIns(LiveRegUnits &LiveUnits,
                             const MachineBasicBlock &MBB) {
   for (const auto &LI : MBB.liveins())
-    LiveUnits.addRegMasked(LI, LaneBitmask::getAll());
+    LiveUnits.addRegMasked(LI);
 }
 
 /// Adds all callee saved registers to \p LiveUnits.

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -728,12 +728,9 @@ void printMBB(raw_ostream &OS, MFPrintState &State,
   if (!MBB.livein_empty()) {
     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
     OS.indent(2) << "liveins: ";
-    bool First = true;
-    for (const Register Reg : MBB.liveins_dbg()) {
-      if (!First)
-        OS << ", ";
-      First = false;
-      OS << printReg(Reg, &TRI);
+    ListSeparator LS;
+    for (const auto &LI : MBB.liveins_dbg()) {
+      OS << LS << printReg(LI, &TRI);
     }
     OS << "\n";
     HasLineAttributes = true;

llvm/lib/CodeGen/MachineBasicBlock.cpp

@@ -427,7 +427,7 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
     OS.indent(2) << "liveins: ";
 
     ListSeparator LS;
-    for (const MCRegister Reg : liveins()) {
+    for (MCRegister Reg : liveins()) {
       OS << LS << printReg(Reg, TRI);
     }
     HasLineAttributes = true;
@@ -656,7 +656,7 @@ bool MachineBasicBlock::isLiveIn(MCRegister Reg, LaneBitmask LaneMask) const {
 Register
 MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
   assert(getParent() && "MBB must be inserted in function");
-  assert(PhysReg && "Expected physreg");
+  assert(PhysReg.isPhysical() && "Expected physreg");
   assert(RC && "Register class is required");
   assert((isEHPad() || this == &getParent()->front()) &&
          "Only the entry block and landing pads can have physreg live ins");