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author
joaosaffran
committed
adding tests
1 parent 5423aba commit a7637a7

6 files changed

+119
-136
lines changed

‎llvm/lib/Target/DirectX/DXILPostOptimizationValidation.cpp

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -7,15 +7,11 @@
77
//===----------------------------------------------------------------------===//
88

99
#include "DXILPostOptimizationValidation.h"
10-
#include "DXILRootSignature.h"
1110
#include "DXILShaderFlags.h"
1211
#include "DirectX.h"
13-
#include "llvm/ADT/STLForwardCompat.h"
1412
#include "llvm/ADT/SmallString.h"
15-
#include "llvm/ADT/iterator_range.h"
1613
#include "llvm/Analysis/DXILMetadataAnalysis.h"
1714
#include "llvm/Analysis/DXILResource.h"
18-
#include "llvm/BinaryFormat/DXContainer.h"
1915
#include "llvm/IR/DiagnosticInfo.h"
2016
#include "llvm/IR/Instructions.h"
2117
#include "llvm/IR/IntrinsicsDirectX.h"
@@ -130,13 +126,10 @@ static uint32_t parameterToRangeType(uint32_t Type) {
130126
switch (Type) {
131127
case llvm::to_underlying(dxbc::RootParameterType::CBV):
132128
return llvm::to_underlying(dxbc::DescriptorRangeType::CBV);
133-
break;
134129
case llvm::to_underlying(dxbc::RootParameterType::SRV):
135130
return llvm::to_underlying(dxbc::DescriptorRangeType::SRV);
136-
break;
137131
case llvm::to_underlying(dxbc::RootParameterType::UAV):
138132
return llvm::to_underlying(dxbc::DescriptorRangeType::UAV);
139-
break;
140133
default:
141134
llvm_unreachable("Root Parameter Type has no Range Type equivalent");
142135
}

‎llvm/test/CodeGen/DirectX/rootsignature-validation-fail.ll renamed to ‎llvm/test/CodeGen/DirectX/rootsignature-validation-fail-cbuffer.ll

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,21 @@
22

33
; CHECK: error: register CB (space=665, register=3) is not defined in Root Signature
44

5+
; Root Signature(
6+
; CBV(b3, space=666, visibility=SHADER_VISIBILITY_ALL)
7+
; DescriptorTable(SRV(t0, space=0, numDescriptors=1), visibility=SHADER_VISIBILITY_ALL)
8+
; DescriptorTable(Sampler(s0, numDescriptors=2), visibility=SHADER_VISIBILITY_VERTEX)
9+
; DescriptorTable(UAV(u0, numDescriptors=unbounded), visibility=SHADER_VISIBILITY_ALL)
10+
511
%__cblayout_CB = type <{ float }>
612

713
@CB.str = private unnamed_addr constant [3 x i8] c"CB\00", align 1
814

915
define void @CSMain() "hlsl.shader"="compute" {
1016
entry:
17+
; cbuffer CB : register(b3, space665) {
18+
; float a;
19+
; }
1120
%CB = tail call target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) @llvm.dx.resource.handlefrombinding(i32 665, i32 3, i32 1, i32 0, i1 false, ptr nonnull @CB.str)
1221
ret void
1322
}

‎llvm/test/CodeGen/DirectX/rootsignature-validation-fail-sampler.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
; RUN: not opt -S -passes='dxil-post-optimization-validation' -mtriple=dxil-pc-shadermodel6.6-compute %s 2>&1 | FileCheck %s
2+
3+
; CHECK: error: register Smp (space=2, register=3) is not defined in Root Signature
4+
5+
; Root Signature(
6+
; CBV(b3, space=666, visibility=SHADER_VISIBILITY_ALL)
7+
; DescriptorTable(SRV(t0, space=0, numDescriptors=1), visibility=SHADER_VISIBILITY_VERTEX)
8+
; DescriptorTable(Sampler(s0, numDescriptors=2), visibility=SHADER_VISIBILITY_ALL)
9+
; DescriptorTable(UAV(u0, numDescriptors=unbounded), visibility=SHADER_VISIBILITY_ALL)
10+
11+
@Smp.str = private unnamed_addr constant [4 x i8] c"Smp\00", align 1
12+
13+
define void @CSMain() "hlsl.shader"="compute" {
14+
entry:
15+
; SamplerState S1 : register(s3, space2);
16+
%Sampler = call target("dx.Sampler", 0) @llvm.dx.resource.handlefrombinding(i32 2, i32 3, i32 1, i32 0, i1 false, ptr nonnull @Smp.str)
17+
18+
ret void
19+
}
20+
21+
!dx.rootsignatures = !{!0}
22+
23+
!0 = !{ptr @CSMain, !1, i32 2}
24+
!1 = !{!2, !3, !5, !7}
25+
!2 = !{!"RootCBV", i32 0, i32 3, i32 666, i32 4}
26+
!3 = !{!"DescriptorTable", i32 1, !4}
27+
!4 = !{!"SRV", i32 1, i32 0, i32 0, i32 -1, i32 4}
28+
!5 = !{!"DescriptorTable", i32 0, !6}
29+
!6 = !{!"Sampler", i32 2, i32 0, i32 0, i32 -1, i32 0}
30+
!7 = !{!"DescriptorTable", i32 0, !8}
31+
!8 = !{!"UAV", i32 -1, i32 0, i32 0, i32 -1, i32 2}

‎llvm/test/CodeGen/DirectX/rootsignature-validation-fail-srv.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
; RUN: not opt -S -passes='dxil-post-optimization-validation' -mtriple=dxil-pc-shadermodel6.6-compute %s 2>&1 | FileCheck %s
2+
3+
; CHECK: error: register SB (space=0, register=0) is not defined in Root Signature
4+
5+
; Root Signature(
6+
; CBV(b3, space=666, visibility=SHADER_VISIBILITY_ALL)
7+
; DescriptorTable(SRV(t0, space=0, numDescriptors=1), visibility=SHADER_VISIBILITY_VERTEX)
8+
; DescriptorTable(Sampler(s0, numDescriptors=2), visibility=SHADER_VISIBILITY_ALL)
9+
; DescriptorTable(UAV(u0, numDescriptors=unbounded), visibility=SHADER_VISIBILITY_ALL)
10+
11+
@SB.str = private unnamed_addr constant [3 x i8] c"SB\00", align 1
12+
13+
define void @CSMain() "hlsl.shader"="compute" {
14+
entry:
15+
; StructuredBuffer<int> In : register(t0, space0);
16+
%SB = tail call target("dx.RawBuffer", i32, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @SB.str)
17+
ret void
18+
}
19+
20+
!dx.rootsignatures = !{!0}
21+
22+
!0 = !{ptr @CSMain, !1, i32 2}
23+
!1 = !{!2, !3, !5, !7}
24+
!2 = !{!"RootCBV", i32 0, i32 3, i32 666, i32 4}
25+
!3 = !{!"DescriptorTable", i32 1, !4}
26+
!4 = !{!"SRV", i32 1, i32 0, i32 0, i32 -1, i32 4}
27+
!5 = !{!"DescriptorTable", i32 0, !6}
28+
!6 = !{!"Sampler", i32 2, i32 0, i32 0, i32 -1, i32 0}
29+
!7 = !{!"DescriptorTable", i32 0, !8}
30+
!8 = !{!"UAV", i32 -1, i32 0, i32 0, i32 -1, i32 2}

‎llvm/test/CodeGen/DirectX/rootsignature-validation-fail-uav.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
; RUN: not opt -S -passes='dxil-post-optimization-validation' -mtriple=dxil-pc-shadermodel6.6-compute %s 2>&1 | FileCheck %s
2+
3+
; CHECK: error: register RWB (space=0, register=4294967295) is not defined in Root Signature
4+
5+
; Root Signature(
6+
; CBV(b3, space=666, visibility=SHADER_VISIBILITY_ALL)
7+
; DescriptorTable(SRV(t0, space=0, numDescriptors=1), visibility=SHADER_VISIBILITY_VERTEX)
8+
; DescriptorTable(Sampler(s0, numDescriptors=2), visibility=SHADER_VISIBILITY_ALL)
9+
; DescriptorTable(UAV(u0, numDescriptors=unbounded), visibility=SHADER_VISIBILITY_ALL)
10+
11+
@RWB.str = private unnamed_addr constant [4 x i8] c"RWB\00", align 1
12+
13+
define void @CSMain() "hlsl.shader"="compute" {
14+
entry:
15+
; RWBuffer<float> UAV : register(u4294967295);
16+
%RWB = tail call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 0, i32 -1, i32 1, i32 0, i1 false, ptr nonnull @RWB.str)
17+
ret void
18+
}
19+
20+
!dx.rootsignatures = !{!0}
21+
22+
!0 = !{ptr @CSMain, !1, i32 2}
23+
!1 = !{!2, !3, !5, !7}
24+
!2 = !{!"RootCBV", i32 0, i32 3, i32 666, i32 4}
25+
!3 = !{!"DescriptorTable", i32 1, !4}
26+
!4 = !{!"SRV", i32 1, i32 0, i32 0, i32 -1, i32 4}
27+
!5 = !{!"DescriptorTable", i32 0, !6}
28+
!6 = !{!"Sampler", i32 2, i32 0, i32 0, i32 -1, i32 0}
29+
!7 = !{!"DescriptorTable", i32 0, !8}
30+
!8 = !{!"UAV", i32 -1, i32 0, i32 0, i32 -1, i32 2}

‎llvm/test/CodeGen/DirectX/rootsignature-validation.ll

Lines changed: 19 additions & 129 deletions
Original file line numberDiff line numberDiff line change
@@ -1,149 +1,39 @@
11
; RUN: opt -S -passes='dxil-post-optimization-validation' -mtriple=dxil-pc-shadermodel6.6-compute %s 2>&1
22
; expected-no-diagnostics
33

4-
;
5-
; Resource Bindings:
6-
;
7-
; Name Type Format Dim ID HLSL Bind Count
8-
; ------------------------------ ---------- ------- ----------- ------- -------------- ---------
9-
; In texture struct r/o T0 t0 1
10-
; Out UAV struct r/w U0 u0 1
11-
; UAV3 UAV struct r/w U1 u1 1
12-
; UAV1 UAV struct r/w U2 u2 1
13-
; UAV UAV struct r/w U3 u4294967294 1
14-
; CB cbuffer NA NA CB0 cb3,space1 1
15-
;
16-
; ModuleID = '../clang/test/SemaHLSL/RootSignature-Validation.hlsl'
17-
target datalayout = "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:32-f64:64-n8:16:32:64"
18-
target triple = "dxilv1.5-unknown-shadermodel6.5-compute"
4+
5+
; Root Signature(
6+
; CBV(b3, space=1, visibility=SHADER_VISIBILITY_ALL)
7+
; DescriptorTable(SRV(t0, space=0, numDescriptors=1), visibility=SHADER_VISIBILITY_ALL)
8+
; DescriptorTable(Sampler(s0, numDescriptors=2), visibility=SHADER_VISIBILITY_VERTEX)
9+
; DescriptorTable(UAV(u0, numDescriptors=unbounded), visibility=SHADER_VISIBILITY_ALL)
1910

2011
%__cblayout_CB = type <{ float }>
21-
%"StructuredBuffer<int32_t>" = type { i32 }
22-
%"RWStructuredBuffer<int32_t>" = type { i32 }
23-
%"RWStructuredBuffer<float>" = type { float }
24-
%CBuffer.CB = type { float }
2512

26-
@CB.cb = local_unnamed_addr global target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) poison
2713
@CB.str = private unnamed_addr constant [3 x i8] c"CB\00", align 1
28-
@.str = private unnamed_addr constant [3 x i8] c"In\00", align 1
29-
@.str.2 = private unnamed_addr constant [4 x i8] c"Out\00", align 1
30-
@.str.4 = private unnamed_addr constant [4 x i8] c"UAV\00", align 1
31-
@.str.6 = private unnamed_addr constant [5 x i8] c"UAV1\00", align 1
32-
@.str.10 = private unnamed_addr constant [5 x i8] c"UAV3\00", align 1
33-
@In = external constant %"StructuredBuffer<int32_t>"
34-
@Out = external constant %"RWStructuredBuffer<int32_t>"
35-
@UAV3 = external constant %"RWStructuredBuffer<float>"
36-
@UAV1 = external constant %"RWStructuredBuffer<float>"
37-
@UAV = external constant %"RWStructuredBuffer<float>"
38-
@CB = external constant %CBuffer.CB
39-
40-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
41-
declare target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) @llvm.dx.resource.handlefrombinding.tdx.CBuffer_tdx.Layout_s___cblayout_CBs_4_0tt(i32, i32, i32, i32, i1, ptr) #0
14+
@Smp.str = private unnamed_addr constant [4 x i8] c"Smp\00", align 1
15+
@SB.str = private unnamed_addr constant [3 x i8] c"SB\00", align 1
16+
@RWB.str = private unnamed_addr constant [4 x i8] c"RWB\00", align 1
4217

43-
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none)
44-
define void @CSMain() local_unnamed_addr #1 {
18+
define void @CSMain() "hlsl.shader"="compute" {
4519
entry:
46-
%CB.cb_h.i.i = tail call target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) @llvm.dx.resource.handlefrombinding.tdx.CBuffer_tdx.Layout_s___cblayout_CBs_4_0tt(i32 1, i32 3, i32 1, i32 0, i1 false, ptr nonnull @CB.str)
47-
store target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) %CB.cb_h.i.i, ptr @CB.cb, align 4
48-
%0 = tail call target("dx.RawBuffer", i32, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str)
49-
%1 = tail call target("dx.RawBuffer", i32, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_1_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str.2)
50-
%2 = tail call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 -2, i32 1, i32 0, i1 false, ptr nonnull @.str.4)
51-
%3 = tail call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 2, i32 1, i32 0, i1 false, ptr nonnull @.str.6)
52-
%4 = call target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32 0, i32 1, i32 1, i32 0, i1 false, ptr @.str.10)
53-
%5 = call { float, float, float, float } @llvm.dx.resource.load.cbufferrow.4.f32.f32.f32.f32.tdx.CBuffer_tdx.Layout_s___cblayout_CBs_4_0tt(target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) %CB.cb_h.i.i, i32 0)
54-
%6 = extractvalue { float, float, float, float } %5, 0
55-
%7 = call { i32, i1 } @llvm.dx.resource.load.rawbuffer.i32.tdx.RawBuffer_i32_0_0t(target("dx.RawBuffer", i32, 0, 0) %0, i32 0, i32 0)
56-
%8 = extractvalue { i32, i1 } %7, 0
57-
%conv.i = sitofp i32 %8 to float
58-
%add.i = fadd reassoc nnan ninf nsz arcp afn float %6, %conv.i
59-
%9 = call { float, i1 } @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %2, i32 0, i32 0)
60-
%10 = extractvalue { float, i1 } %9, 0
61-
%add2.i = fadd reassoc nnan ninf nsz arcp afn float %add.i, %10
62-
%11 = call { float, i1 } @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %3, i32 0, i32 0)
63-
%12 = extractvalue { float, i1 } %11, 0
64-
%add4.i = fadd reassoc nnan ninf nsz arcp afn float %add2.i, %12
65-
%13 = call { float, i1 } @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %4, i32 0, i32 0)
66-
%14 = extractvalue { float, i1 } %13, 0
67-
%add6.i = fadd reassoc nnan ninf nsz arcp afn float %add4.i, %14
68-
%conv7.i = fptosi float %add6.i to i32
69-
call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_i32_1_0t.i32(target("dx.RawBuffer", i32, 1, 0) %1, i32 0, i32 0, i32 %conv7.i)
70-
ret void
71-
}
72-
73-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
74-
declare target("dx.RawBuffer", i32, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_0_0t(i32, i32, i32, i32, i1, ptr) #0
75-
76-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
77-
declare target("dx.RawBuffer", i32, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_1_0t(i32, i32, i32, i32, i1, ptr) #0
78-
79-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
80-
declare target("dx.RawBuffer", float, 1, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t(i32, i32, i32, i32, i1, ptr) #0
81-
82-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
83-
declare ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i32_1_0t(target("dx.RawBuffer", i32, 1, 0), i32) #0
8420

85-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
86-
declare ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i32_0_0t(target("dx.RawBuffer", i32, 0, 0), i32) #0
21+
%CB = tail call target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) @llvm.dx.resource.handlefrombinding(i32 1, i32 3, i32 1, i32 0, i1 false, ptr nonnull @CB.str)
22+
%Sampler = call target("dx.Sampler", 0) @llvm.dx.resource.handlefrombinding(i32 2, i32 3, i32 1, i32 0, i1 false, ptr nonnull @Smp.str)
23+
%SB = tail call target("dx.RawBuffer", i32, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i32_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @SB.str)
24+
%RWB = tail call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding.tdx.TypedBuffer_f32_1_0_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @RWB.str)
8725

88-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
89-
declare ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i32) #0
90-
91-
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
92-
declare { i32, i1 } @llvm.dx.resource.load.rawbuffer.i32.tdx.RawBuffer_i32_0_0t(target("dx.RawBuffer", i32, 0, 0), i32, i32) #2
93-
94-
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
95-
declare { float, i1 } @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0), i32, i32) #2
96-
97-
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
98-
declare void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_i32_1_0t.i32(target("dx.RawBuffer", i32, 1, 0), i32, i32, i32) #3
99-
100-
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
101-
declare { float, float, float, float } @llvm.dx.resource.load.cbufferrow.4.f32.f32.f32.f32.tdx.CBuffer_tdx.Layout_s___cblayout_CBs_4_0tt(target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)), i32) #2
102-
103-
; uselistorder directives
104-
uselistorder ptr @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_1_0t, { 2, 1, 0 }
105-
uselistorder ptr @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_1_0t, { 2, 1, 0 }
106-
107-
attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
108-
attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="8,8,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
109-
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(read) }
110-
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) }
26+
ret void
27+
}
11128

11229
!dx.rootsignatures = !{!0}
113-
!llvm.module.flags = !{!9, !10}
114-
!dx.valver = !{!11}
115-
!llvm.ident = !{!12}
116-
!dx.shaderModel = !{!13}
117-
!dx.version = !{!14}
118-
!dx.resources = !{!15}
119-
!dx.entryPoints = !{!26}
12030

12131
!0 = !{ptr @CSMain, !1, i32 2}
12232
!1 = !{!2, !3, !5, !7}
12333
!2 = !{!"RootCBV", i32 0, i32 3, i32 1, i32 4}
12434
!3 = !{!"DescriptorTable", i32 0, !4}
125-
!4 = !{!"SRV", i32 1, i32 0, i32 0, i32 -1, i32 4}
126-
!5 = !{!"DescriptorTable", i32 1, !6}
127-
!6 = !{!"Sampler", i32 2, i32 0, i32 0, i32 -1, i32 0}
35+
!4 = !{!"SRV", i32 1, i32 0, i32 0, i32 -1, i32 0}
36+
!5 = !{!"DescriptorTable", i32 0, !6}
37+
!6 = !{!"Sampler", i32 5, i32 3, i32 2, i32 -1, i32 0}
12838
!7 = !{!"DescriptorTable", i32 0, !8}
12939
!8 = !{!"UAV", i32 -1, i32 0, i32 0, i32 -1, i32 2}
130-
!9 = !{i32 1, !"wchar_size", i32 4}
131-
!10 = !{i32 7, !"frame-pointer", i32 2}
132-
!11 = !{i32 1, i32 8}
133-
!12 = !{!"clang version 21.0.0git (https://github.com/joaosaffran/llvm-project.git c16f15b4cd469a3f6efc2e4b0e098190d7fd0787)"}
134-
!13 = !{!"cs", i32 6, i32 5}
135-
!14 = !{i32 1, i32 5}
136-
!15 = !{!16, !19, !24, null}
137-
!16 = !{!17}
138-
!17 = !{i32 0, ptr @In, !"In", i32 0, i32 0, i32 1, i32 12, i32 0, !18}
139-
!18 = !{i32 1, i32 4}
140-
!19 = !{!20, !21, !22, !23}
141-
!20 = !{i32 0, ptr @Out, !"Out", i32 0, i32 0, i32 1, i32 12, i1 false, i1 false, i1 false, !18}
142-
!21 = !{i32 1, ptr @UAV3, !"UAV3", i32 0, i32 1, i32 1, i32 12, i1 false, i1 false, i1 false, !18}
143-
!22 = !{i32 2, ptr @UAV1, !"UAV1", i32 0, i32 2, i32 1, i32 12, i1 false, i1 false, i1 false, !18}
144-
!23 = !{i32 3, ptr @UAV, !"UAV", i32 0, i32 -2, i32 1, i32 12, i1 false, i1 false, i1 false, !18}
145-
!24 = !{!25}
146-
!25 = !{i32 0, ptr @CB, !"CB", i32 1, i32 3, i32 1, i32 4, null}
147-
!26 = !{ptr @CSMain, !"CSMain", null, !15, !27}
148-
!27 = !{i32 0, i64 16, i32 4, !28}
149-
!28 = !{i32 8, i32 8, i32 1}

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