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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s |
| 3 | + |
| 4 | +define i64 @strlen16_vec(ptr %s) { |
| 5 | +; CHECK-LABEL: strlen16_vec: |
| 6 | +; CHECK: # %bb.0: # %entry |
| 7 | +; CHECK-NEXT: li a1, 0 |
| 8 | +; CHECK-NEXT: li a2, 16 |
| 9 | +; CHECK-NEXT: li a3, -1 |
| 10 | +; CHECK-NEXT: li a4, 16 |
| 11 | +; CHECK-NEXT: j .LBB0_2 |
| 12 | +; CHECK-NEXT: .LBB0_1: # %while.body |
| 13 | +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 |
| 14 | +; CHECK-NEXT: add a1, a6, a1 |
| 15 | +; CHECK-NEXT: bne a5, a3, .LBB0_5 |
| 16 | +; CHECK-NEXT: .LBB0_2: # %while.cond |
| 17 | +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 |
| 18 | +; CHECK-NEXT: bne a4, a2, .LBB0_5 |
| 19 | +; CHECK-NEXT: # %bb.3: # %while.body |
| 20 | +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 |
| 21 | +; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma |
| 22 | +; CHECK-NEXT: vle16ff.v v8, (a0) |
| 23 | +; CHECK-NEXT: csrr a4, vl |
| 24 | +; CHECK-NEXT: vmseq.vi v8, v8, 0 |
| 25 | +; CHECK-NEXT: vfirst.m a5, v8 |
| 26 | +; CHECK-NEXT: mv a6, a4 |
| 27 | +; CHECK-NEXT: beq a5, a3, .LBB0_1 |
| 28 | +; CHECK-NEXT: # %bb.4: # %while.body |
| 29 | +; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 |
| 30 | +; CHECK-NEXT: mv a6, a5 |
| 31 | +; CHECK-NEXT: j .LBB0_1 |
| 32 | +; CHECK-NEXT: .LBB0_5: # %while.end |
| 33 | +; CHECK-NEXT: mv a0, a1 |
| 34 | +; CHECK-NEXT: ret |
| 35 | +entry: |
| 36 | + br label %while.cond |
| 37 | + |
| 38 | +while.cond: ; preds = %while.body, %entry |
| 39 | + %new_vl.0 = phi i64 [ 16, %entry ], [ %2, %while.body ] |
| 40 | + %len.0 = phi i64 [ 0, %entry ], [ %len.1, %while.body ] |
| 41 | + %cmp = icmp eq i64 %new_vl.0, 16 |
| 42 | + br i1 %cmp, label %while.body, label %while.end |
| 43 | + |
| 44 | +while.body: ; preds = %while.cond |
| 45 | + %0 = tail call { <vscale x 4 x i16>, i64 } @llvm.riscv.vleff.nxv4i16.i64(<vscale x 4 x i16> poison, ptr %s, i64 16) |
| 46 | + %1 = extractvalue { <vscale x 4 x i16>, i64 } %0, 0 |
| 47 | + %2 = extractvalue { <vscale x 4 x i16>, i64 } %0, 1 |
| 48 | + %3 = tail call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16.i64(<vscale x 4 x i16> %1, i16 0, i64 %2) |
| 49 | + %4 = tail call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> %3, i64 %2) |
| 50 | + %cmp1 = icmp eq i64 %4, -1 |
| 51 | + %.13 = select i1 %cmp1, i64 %2, i64 %4 |
| 52 | + %len.1 = add i64 %.13, %len.0 |
| 53 | + br i1 %cmp1, label %while.cond, label %while.end |
| 54 | + |
| 55 | +while.end: ; preds = %while.body, %while.cond |
| 56 | + %len.2 = phi i64 [ %len.1, %while.body ], [ %len.0, %while.cond ] |
| 57 | + ret i64 %len.2 |
| 58 | +} |
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