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Merge amd-gfx12 and amd-gfx into amd-gfx-gfx12
2 parents aa780d9 + 8f9631f commit a8b1415

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9 files changed

+686
-33
lines changed

9 files changed

+686
-33
lines changed

‎llvm/include/llvm/Config/llvm-config.h.cmake‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 545528
19+
#define LLVM_MAIN_REVISION 546475
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/include/llvm/IR/DebugInfoMetadata.h‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include "llvm/ADT/Hashing.h"
1919
#include "llvm/ADT/PointerUnion.h"
2020
#include "llvm/ADT/STLExtras.h"
21+
#include "llvm/ADT/SmallBitVector.h"
2122
#include "llvm/ADT/SmallVector.h"
2223
#include "llvm/ADT/StringRef.h"
2324
#include "llvm/ADT/iterator_range.h"
@@ -4209,6 +4210,29 @@ class DIExpression : public MDNode {
42094210
unsigned ArgNo,
42104211
Type *NewArgType = nullptr);
42114212

4213+
/// Create a copy of \p Expr updated to reflect that the debug operands
4214+
/// whose indexes are set in \p SpilledOpIndexes were spilled to the stack,
4215+
/// which is in the \p SpillAddrSpace address space.
4216+
///
4217+
/// Handles both New and Old expressions, including Old expressions without
4218+
/// an explicit DW_OP_LLVM_arg.
4219+
static const DIExpression *spillArgs(const DIExpression *Expr,
4220+
SmallBitVector SpilledOpIndexes,
4221+
unsigned SpillAddrSpace);
4222+
4223+
/// Create a copy of \p Expr with an explicit indirection if \p IsIndirect, in
4224+
/// preparation for changing the referring intrinsic from one with the concept
4225+
/// of "IsIndirect" to one without it.
4226+
///
4227+
/// Handles both Old and New expressions, being a no-op for New expressions
4228+
/// which always include indirection explicitly.
4229+
static const DIExpression *foldIntrinsicIndirection(const DIExpression *Expr,
4230+
bool IsIndirect);
4231+
4232+
/// Create a copy of \p Expr updated to be suitable for use by DBG_INSTR_REF.
4233+
static const DIExpression *convertForInstrRef(const DIExpression *Expr,
4234+
bool IsIndirect);
4235+
42124236
/// Create a copy of \p Expr with each instance of
42134237
/// `DW_OP_LLVM_arg, \p OldArg` replaced with `DW_OP_LLVM_arg, \p NewArg`,
42144238
/// and each instance of `DW_OP_LLVM_arg, Arg` with `DW_OP_LLVM_arg, Arg - 1`

‎llvm/lib/CodeGen/MachineInstr.cpp‎

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2426,20 +2426,12 @@ static const DIExpression *computeExprForSpill(
24262426
"Expected inlined-at fields to agree");
24272427

24282428
const DIExpression *Expr = MI.getDebugExpression();
2429-
if (MI.isIndirectDebugValue()) {
2430-
assert(MI.getDebugOffset().getImm() == 0 &&
2431-
"DBG_VALUE with nonzero offset");
2432-
Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2433-
} else if (MI.isDebugValueList()) {
2434-
// We will replace the spilled register with a frame index, so
2435-
// immediately deref all references to the spilled register.
2436-
std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2437-
for (const MachineOperand *Op : SpilledOperands) {
2438-
unsigned OpIdx = MI.getDebugOperandIndex(Op);
2439-
Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2440-
}
2441-
}
2442-
return Expr;
2429+
SmallBitVector SpilledOpIndexes(MI.getNumDebugOperands());
2430+
for (const MachineOperand *Op : SpilledOperands)
2431+
SpilledOpIndexes.set(MI.getDebugOperandIndex(Op));
2432+
unsigned SpillAddrSpace = MI.getMF()->getDataLayout().getAllocaAddrSpace();
2433+
2434+
return DIExpression::spillArgs(Expr, SpilledOpIndexes, SpillAddrSpace);
24432435
}
24442436
static const DIExpression *computeExprForSpill(const MachineInstr &MI,
24452437
Register SpillReg) {

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -813,14 +813,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
813813
return EmitDbgValueFromSingleOp(SD, VRBaseMap);
814814
}
815815

816-
// Immediately fold any indirectness from the LLVM-IR intrinsic into the
817-
// expression:
818-
if (SD->isIndirect())
819-
Expr = DIExpression::append(Expr, dwarf::DW_OP_deref);
820-
// If this is not already a variadic expression, it must be modified to become
821-
// one.
822-
if (!SD->isVariadic())
823-
Expr = DIExpression::convertToVariadicExpression(Expr);
816+
Expr = DIExpression::convertForInstrRef(Expr, SD->isIndirect());
824817

825818
SmallVector<MachineOperand> MOs;
826819

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp‎

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -6088,16 +6088,7 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
60886088
/* isKill */ false, /* isDead */ false,
60896089
/* isUndef */ false, /* isEarlyClobber */ false,
60906090
/* SubReg */ 0, /* isDebug */ true)});
6091-
6092-
auto *NewDIExpr = FragExpr;
6093-
// We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
6094-
// the DIExpression.
6095-
if (Indirect)
6096-
NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
6097-
if (NewDIExpr->holdsOldElements()) {
6098-
SmallVector<uint64_t, 2> Ops({dwarf::DW_OP_LLVM_arg, 0});
6099-
NewDIExpr = DIExpression::prependOpcodes(NewDIExpr, Ops);
6100-
}
6091+
auto *NewDIExpr = DIExpression::convertForInstrRef(FragExpr, Indirect);
61016092
return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr);
61026093
} else {
61036094
// Create a completely standard DBG_VALUE.

‎llvm/lib/IR/DebugInfoMetadata.cpp‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2442,6 +2442,48 @@ DIExpression *DIExpression::appendNewOpsToArg(const DIExpression *Expr,
24422442
return Builder.intoExpression();
24432443
}
24442444

2445+
const DIExpression *DIExpression::spillArgs(const DIExpression *Expr,
2446+
SmallBitVector SpilledOpIndexes,
2447+
unsigned SpillAddrSpace) {
2448+
if (auto ExprOps = Expr->getNewElementsRef()) {
2449+
DIExprBuilder Builder(Expr->getContext());
2450+
auto *AllocaPtrTy = PointerType::get(Expr->getContext(), SpillAddrSpace);
2451+
for (auto Op : *ExprOps) {
2452+
DIOp::Arg *AsArg = std::get_if<DIOp::Arg>(&Op);
2453+
if (AsArg && SpilledOpIndexes.test(AsArg->getIndex())) {
2454+
Builder.append<DIOp::Arg>(AsArg->getIndex(), AllocaPtrTy);
2455+
Builder.append<DIOp::Deref>(AsArg->getResultType());
2456+
} else {
2457+
Builder.append(Op);
2458+
}
2459+
}
2460+
return Builder.intoExpression();
2461+
}
2462+
2463+
std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2464+
for (unsigned OpIdx : SpilledOpIndexes.set_bits())
2465+
Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2466+
return Expr;
2467+
}
2468+
2469+
const DIExpression *
2470+
DIExpression::foldIntrinsicIndirection(const DIExpression *Expr,
2471+
bool IsIndirect) {
2472+
if (!IsIndirect || Expr->holdsNewElements())
2473+
return Expr;
2474+
return DIExpression::append(Expr, dwarf::DW_OP_deref);
2475+
}
2476+
2477+
const DIExpression *DIExpression::convertForInstrRef(const DIExpression *Expr,
2478+
bool IsIndirect) {
2479+
// Immediately fold any indirectness from the LLVM-IR intrinsic into the
2480+
// expression:
2481+
Expr = DIExpression::foldIntrinsicIndirection(Expr, IsIndirect);
2482+
// If this is not already a variadic expression, it must be modified to become
2483+
// one.
2484+
return DIExpression::convertToVariadicExpression(Expr);
2485+
}
2486+
24452487
DIExpression *DIExpression::replaceArg(const DIExpression *Expr,
24462488
uint64_t OldArg, uint64_t NewArg) {
24472489
assert(Expr && "Can't replace args in this expression");

‎llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-pointer-parameters-isel.ll‎

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,143 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O0 %s
3+
; RUN: llc -O1 -mtriple=amdgcn -mcpu=gfx1100 -start-before=amdgpu-isel -stop-after=amdgpu-isel < %s | FileCheck --check-prefixes=CHECK-O1 %s
4+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
5+
target triple = "amdgcn-amd-amdhsa"
6+
7+
define void @_QFPadd(ptr %0, ptr %1) #0 !dbg !12 {
8+
; CHECK-O0-LABEL: name: _QFPadd
9+
; CHECK-O0: bb.0 (%ir-block.2):
10+
; CHECK-O0-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
11+
; CHECK-O0-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
12+
; CHECK-O0-NEXT: {{ $}}
13+
; CHECK-O0-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
14+
; CHECK-O0-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
15+
; CHECK-O0-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
16+
; CHECK-O0-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17+
; CHECK-O0-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1
18+
; CHECK-O0-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1
19+
; CHECK-O0-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
20+
; CHECK-O0-NEXT: DBG_VALUE [[COPY4]], 0, !9, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8
21+
; CHECK-O0-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
22+
; CHECK-O0-NEXT: DBG_VALUE [[COPY5]], 0, !7, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), debug-location !8
23+
; CHECK-O0-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10
24+
; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0)
25+
; CHECK-O0-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10
26+
; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1)
27+
; CHECK-O0-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10
28+
; CHECK-O0-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_I32_e64_]], implicit-def dead $scc, debug-location !10
29+
; CHECK-O0-NEXT: $vcc_lo = COPY [[S_AND_B32_]], debug-location !10
30+
; CHECK-O0-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10
31+
; CHECK-O0-NEXT: S_BRANCH %bb.1, debug-location !10
32+
; CHECK-O0-NEXT: {{ $}}
33+
; CHECK-O0-NEXT: bb.1 (%ir-block.6):
34+
; CHECK-O0-NEXT: successors: %bb.3(0x80000000)
35+
; CHECK-O0-NEXT: {{ $}}
36+
; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0)
37+
; CHECK-O0-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
38+
; CHECK-O0-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_]], 0, implicit $exec, debug-location !11
39+
; CHECK-O0-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1)
40+
; CHECK-O0-NEXT: S_BRANCH %bb.3, debug-location !10
41+
; CHECK-O0-NEXT: {{ $}}
42+
; CHECK-O0-NEXT: bb.2 (%ir-block.9):
43+
; CHECK-O0-NEXT: successors: %bb.3(0x80000000)
44+
; CHECK-O0-NEXT: {{ $}}
45+
; CHECK-O0-NEXT: [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1)
46+
; CHECK-O0-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
47+
; CHECK-O0-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !12
48+
; CHECK-O0-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1)
49+
; CHECK-O0-NEXT: S_BRANCH %bb.3, debug-location !10
50+
; CHECK-O0-NEXT: {{ $}}
51+
; CHECK-O0-NEXT: bb.3 (%ir-block.12):
52+
; CHECK-O0-NEXT: SI_RETURN debug-location !13
53+
;
54+
; CHECK-O1-LABEL: name: _QFPadd
55+
; CHECK-O1: bb.0 (%ir-block.2):
56+
; CHECK-O1-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
57+
; CHECK-O1-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
58+
; CHECK-O1-NEXT: {{ $}}
59+
; CHECK-O1-NEXT: DBG_PHI $vgpr1, 6
60+
; CHECK-O1-NEXT: DBG_PHI $vgpr0, 5
61+
; CHECK-O1-NEXT: DBG_PHI $vgpr3, 3
62+
; CHECK-O1-NEXT: DBG_PHI $vgpr2, 2
63+
; CHECK-O1-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr3
64+
; CHECK-O1-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
65+
; CHECK-O1-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
66+
; CHECK-O1-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr0
67+
; CHECK-O1-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1, debug-instr-number 1
68+
; CHECK-O1-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1, debug-instr-number 4
69+
; CHECK-O1-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
70+
; CHECK-O1-NEXT: DBG_INSTR_REF !9, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(2, 0), dbg-instr-ref(3, 0), debug-location !8
71+
; CHECK-O1-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]]
72+
; CHECK-O1-NEXT: DBG_INSTR_REF !7, !DIExpression(DIOpArg(0, i32), DIOpArg(1, i32), DIOpComposite(2, ptr), DIOpDeref(ptr)), dbg-instr-ref(5, 0), dbg-instr-ref(6, 0), debug-location !8
73+
; CHECK-O1-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], debug-location !10
74+
; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY6]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.0)
75+
; CHECK-O1-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], debug-location !10
76+
; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY7]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !10 :: (load (s32) from %ir.1)
77+
; CHECK-O1-NEXT: [[V_CMP_LE_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_I32_e64 killed [[FLAT_LOAD_DWORD]], killed [[FLAT_LOAD_DWORD1]], implicit $exec, debug-location !10
78+
; CHECK-O1-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, killed [[V_CMP_LE_I32_e64_]], implicit-def dead $scc, debug-location !10
79+
; CHECK-O1-NEXT: $vcc_lo = COPY [[S_AND_B32_]], debug-location !10
80+
; CHECK-O1-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc, debug-location !10
81+
; CHECK-O1-NEXT: S_BRANCH %bb.1, debug-location !10
82+
; CHECK-O1-NEXT: {{ $}}
83+
; CHECK-O1-NEXT: bb.1 (%ir-block.6):
84+
; CHECK-O1-NEXT: successors: %bb.3(0x80000000)
85+
; CHECK-O1-NEXT: {{ $}}
86+
; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD2:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (load (s32) from %ir.0)
87+
; CHECK-O1-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1
88+
; CHECK-O1-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD2]], killed [[S_MOV_B32_]], 0, implicit $exec, debug-location !11
89+
; CHECK-O1-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !11 :: (store (s32) into %ir.1)
90+
; CHECK-O1-NEXT: S_BRANCH %bb.3, debug-location !10
91+
; CHECK-O1-NEXT: {{ $}}
92+
; CHECK-O1-NEXT: bb.2 (%ir-block.9):
93+
; CHECK-O1-NEXT: successors: %bb.3(0x80000000)
94+
; CHECK-O1-NEXT: {{ $}}
95+
; CHECK-O1-NEXT: [[FLAT_LOAD_DWORD3:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (load (s32) from %ir.1)
96+
; CHECK-O1-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1
97+
; CHECK-O1-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[FLAT_LOAD_DWORD3]], killed [[S_MOV_B32_1]], 0, implicit $exec, debug-location !12
98+
; CHECK-O1-NEXT: FLAT_STORE_DWORD [[COPY4]], killed [[V_ADD_U32_e64_1]], 0, 0, implicit $exec, implicit $flat_scr, debug-location !12 :: (store (s32) into %ir.1)
99+
; CHECK-O1-NEXT: {{ $}}
100+
; CHECK-O1-NEXT: bb.3 (%ir-block.12):
101+
; CHECK-O1-NEXT: SI_RETURN debug-location !13
102+
#dbg_declare(ptr %0, !17, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18)
103+
#dbg_declare(ptr %1, !19, !DIExpression(DIOpArg(0, ptr), DIOpDeref(ptr)), !18)
104+
%3 = load i32, ptr %0, align 4, !dbg !20
105+
%4 = load i32, ptr %1, align 4, !dbg !20
106+
%5 = icmp sgt i32 %3, %4, !dbg !20
107+
br i1 %5, label %6, label %9, !dbg !20
108+
109+
6: ; preds = %2
110+
%7 = load i32, ptr %0, align 4, !dbg !21
111+
%8 = add i32 %7, 1, !dbg !21
112+
store i32 %8, ptr %1, align 4, !dbg !21
113+
br label %12, !dbg !20
114+
115+
9: ; preds = %2
116+
%10 = load i32, ptr %1, align 4, !dbg !22
117+
%11 = add i32 %10, 1, !dbg !22
118+
store i32 %11, ptr %1, align 4, !dbg !22
119+
br label %12, !dbg !20
120+
121+
12: ; preds = %9, %6
122+
ret void, !dbg !23
123+
}
124+
125+
126+
!llvm.module.flags = !{!2}
127+
!llvm.dbg.cu = !{!6}
128+
129+
!2 = !{i32 2, !"Debug Info Version", i32 3}
130+
!6 = distinct !DICompileUnit(language: DW_LANG_Fortran95, file: !7, producer: "flang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug)
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!7 = !DIFile(filename: "target14.f90", directory: "")
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!11 = !{i32 2, i32 0}
133+
!12 = distinct !DISubprogram(name: "add", linkageName: "_QFPadd", scope: !7, file: !7, line: 16, type: !14, scopeLine: 16, spFlags: DISPFlagDefinition, unit: !6)
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!14 = !DISubroutineType(cc: DW_CC_normal, types: !15)
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!15 = !{null, !16, !16}
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!16 = !DIBasicType(name: "integer", size: 32, encoding: DW_ATE_signed)
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!17 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !7, line: 17, type: !16)
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!18 = !DILocation(line: 16, column: 7, scope: !12)
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!19 = !DILocalVariable(name: "b", arg: 2, scope: !12, file: !7, line: 17, type: !16)
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!20 = !DILocation(line: 20, column: 7, scope: !12)
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!21 = !DILocation(line: 21, column: 7, scope: !12)
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!22 = !DILocation(line: 23, column: 7, scope: !12)
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!23 = !DILocation(line: 25, column: 7, scope: !12)

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