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Inline bitcast node creation.
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+6
-4
lines changed

1 file changed

+6
-4
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4865,22 +4865,24 @@ static SDValue getBitwiseToSrcModifierOp(SDValue N,
48654865
EVT VT = RHS.getValueType();
48664866
EVT FVT = getFloatVT(VT);
48674867
SDLoc SL = SDLoc(N);
4868-
SDValue BC = DAG.getNode(ISD::BITCAST, SL, FVT, LHS);
48694868

48704869
switch (Opc) {
48714870
case ISD::XOR:
48724871
if (CRHS->getAPIntValue().isSignMask())
4873-
return DAG.getNode(ISD::FNEG, SL, FVT, BC);
4872+
return DAG.getNode(ISD::FNEG, SL, FVT,
4873+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48744874
break;
48754875
case ISD::OR:
48764876
if (CRHS->getAPIntValue().isSignMask()) {
4877-
SDValue Abs = DAG.getNode(ISD::FABS, SL, FVT, BC);
4877+
SDValue Abs = DAG.getNode(ISD::FABS, SL, FVT,
4878+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48784879
return DAG.getNode(ISD::FNEG, SL, FVT, Abs);
48794880
}
48804881
break;
48814882
case ISD::AND:
48824883
if (CRHS->getAPIntValue().isMaxSignedValue())
4883-
return DAG.getNode(ISD::FABS, SL, FVT, BC);
4884+
return DAG.getNode(ISD::FABS, SL, FVT,
4885+
DAG.getNode(ISD::BITCAST, SL, FVT, LHS));
48844886
break;
48854887
default:
48864888
return SDValue();

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