Added timeline to ensure specific instructuion execution is tested

Author: r-belenov

llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s

@@ -1,17 +1,17 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 --timeline -iterations=1 < %s | FileCheck %s
 
-# LLVM-MCA-LATENCY 100
+# LLVM-MCA-LATENCY 20
 add a0, a0, a0
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      1
-# CHECK-NEXT: Total Cycles:      101
+# CHECK-NEXT: Total Cycles:      21
 # CHECK-NEXT: Total uOps:        1
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.01
-# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: uOps Per Cycle:    0.05
+# CHECK-NEXT: IPC:               0.05
 # CHECK-NEXT: Block RThroughput: 0.5
 
 # CHECK:      Instruction Info:
@@ -42,3 +42,18 @@ add a0, a0, a0
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     add       a0, a0, a0
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789
+# CHECK-NEXT: Index     0123456789          0
+
+# CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeeE   add     a0, a0, a0
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       add  a0, a0, a0