- Fix comments in AArch64ISelDAGToDAG & ArmSMEToLLVM

Author: kmclaughlin-arm

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -940,9 +940,8 @@ bool AArch64DAGToDAGISel::SelectRDVLImm(SDValue N, SDValue &Imm) {
   return false;
 }
 
-// Given cntsd = (rdsvl, #1) >> 3, attempt to return a suitable multiplier
-// for RDSVL to calculate the streaming vector length in bytes * N. i.e.
-//   rdsvl, #(ShlImm - 3)
+// Given `cntsd = (rdsvl, #1) >> 3`, attempt to return a suitable multiplier
+// for RDSVL to calculate `cntsd << N`, i.e. `rdsvl, #(N - 3)`.
 template <signed Low, signed High>
 bool AArch64DAGToDAGISel::SelectRDSVLShiftImm(SDValue N, SDValue &Imm) {
   if (!isa<ConstantSDNode>(N))

mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp

@@ -831,9 +831,9 @@ struct OuterProductWideningOpConversion
 /// is converted to:
 ///
 ///   %cnt = "arm_sme.intr.cntsd"() : () -> i64
-///   %0 = arith.constant 4 : i64
-///   %1 = arith.muli %cnt, %0 : i64
-///   %2 = arith.index_cast %1 : i64 to index
+///   %scale = arith.constant 4 : index
+///   %cntIndex = arith.index_cast %cnt : i64 to index
+///   %0 = arith.muli %cntIndex, %scale : index
 ///
 struct StreamingVLOpConversion
     : public ConvertArmSMEOpToLLVMPattern<arm_sme::StreamingVLOp,