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[LLVM][CodeGen][SVE] rev(whilelo(a,b)) -> whilehi(b,a). (#88294)
Add similar isel patterns for lt, gt and hi comparison types.
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3 files changed

+780
-19
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3 files changed

+780
-19
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -2037,15 +2037,15 @@ let Predicates = [HasSVEorSME] in {
20372037
defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
20382038
defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne", SETUNE, SETNE, SETUNE, SETNE>;
20392039

2040-
defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt", int_aarch64_sve_whilelt>;
2041-
defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele", int_aarch64_sve_whilele>;
2042-
defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo", int_aarch64_sve_whilelo>;
2043-
defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels", int_aarch64_sve_whilels>;
2040+
defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt", int_aarch64_sve_whilelt, int_aarch64_sve_whilegt>;
2041+
defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele", int_aarch64_sve_whilele, null_frag>;
2042+
defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo", int_aarch64_sve_whilelo, int_aarch64_sve_whilehi>;
2043+
defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels", int_aarch64_sve_whilels, null_frag>;
20442044

2045-
defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt", int_aarch64_sve_whilelt>;
2046-
defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele", int_aarch64_sve_whilele>;
2047-
defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo", int_aarch64_sve_whilelo>;
2048-
defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels", int_aarch64_sve_whilels>;
2045+
defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt", int_aarch64_sve_whilelt, int_aarch64_sve_whilegt>;
2046+
defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele", int_aarch64_sve_whilele, null_frag>;
2047+
defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo", int_aarch64_sve_whilelo, int_aarch64_sve_whilehi>;
2048+
defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels", int_aarch64_sve_whilels, null_frag>;
20492049

20502050
def CTERMEQ_WW : sve_int_cterm<0b0, 0b0, "ctermeq", GPR32>;
20512051
def CTERMNE_WW : sve_int_cterm<0b0, 0b1, "ctermne", GPR32>;
@@ -3792,15 +3792,15 @@ let Predicates = [HasSVE2orSME] in {
37923792
defm TBX_ZZZ : sve2_int_perm_tbx<"tbx", 0b01, int_aarch64_sve_tbx>;
37933793

37943794
// SVE2 integer compare scalar count and limit
3795-
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege>;
3796-
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt>;
3797-
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs>;
3798-
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi>;
3799-
3800-
defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege>;
3801-
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", int_aarch64_sve_whilegt>;
3802-
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", int_aarch64_sve_whilehs>;
3803-
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", int_aarch64_sve_whilehi>;
3795+
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege, null_frag>;
3796+
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt, int_aarch64_sve_whilelt>;
3797+
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs, null_frag>;
3798+
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi, int_aarch64_sve_whilelo>;
3799+
3800+
defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege, null_frag>;
3801+
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", int_aarch64_sve_whilegt, int_aarch64_sve_whilelt>;
3802+
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", int_aarch64_sve_whilehs, null_frag>;
3803+
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", int_aarch64_sve_whilehi, int_aarch64_sve_whilelo>;
38043804

38053805
// SVE2 pointer conflict compare
38063806
defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr", "int_aarch64_sve_whilewr">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5387,7 +5387,8 @@ class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm,
53875387
let isWhile = 1;
53885388
}
53895389

5390-
multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> {
5390+
multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op,
5391+
SDPatternOperator rev_op> {
53915392
def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>;
53925393
def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>;
53935394
def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>;
@@ -5397,9 +5398,19 @@ multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> {
53975398
def : SVE_2_Op_Pat<nxv8i1, op, i32, i32, !cast<Instruction>(NAME # _H)>;
53985399
def : SVE_2_Op_Pat<nxv4i1, op, i32, i32, !cast<Instruction>(NAME # _S)>;
53995400
def : SVE_2_Op_Pat<nxv2i1, op, i32, i32, !cast<Instruction>(NAME # _D)>;
5401+
5402+
def : Pat<(nxv16i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
5403+
(!cast<Instruction>(NAME # "_B") $op1, $op2)>;
5404+
def : Pat<(nxv8i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
5405+
(!cast<Instruction>(NAME # "_H") $op1, $op2)>;
5406+
def : Pat<(nxv4i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
5407+
(!cast<Instruction>(NAME # "_S") $op1, $op2)>;
5408+
def : Pat<(nxv2i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
5409+
(!cast<Instruction>(NAME # "_D") $op1, $op2)>;
54005410
}
54015411

5402-
multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> {
5412+
multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op,
5413+
SDPatternOperator rev_op> {
54035414
def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>;
54045415
def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>;
54055416
def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>;
@@ -5409,6 +5420,15 @@ multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> {
54095420
def : SVE_2_Op_Pat<nxv8i1, op, i64, i64, !cast<Instruction>(NAME # _H)>;
54105421
def : SVE_2_Op_Pat<nxv4i1, op, i64, i64, !cast<Instruction>(NAME # _S)>;
54115422
def : SVE_2_Op_Pat<nxv2i1, op, i64, i64, !cast<Instruction>(NAME # _D)>;
5423+
5424+
def : Pat<(nxv16i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
5425+
(!cast<Instruction>(NAME # "_B") $op1, $op2)>;
5426+
def : Pat<(nxv8i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
5427+
(!cast<Instruction>(NAME # "_H") $op1, $op2)>;
5428+
def : Pat<(nxv4i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
5429+
(!cast<Instruction>(NAME # "_S") $op1, $op2)>;
5430+
def : Pat<(nxv2i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
5431+
(!cast<Instruction>(NAME # "_D") $op1, $op2)>;
54125432
}
54135433

54145434
class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,

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