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lines changed Original file line number Diff line number Diff line change @@ -2106,9 +2106,7 @@ void CodeGenRegBank::computeRegUnitSets() {
21062106
21072107 // For each register class, list the UnitSets that are supersets.
21082108 RegClassUnitSets.resize (RegClasses.size ());
2109- int RCIdx = -1 ;
21102109 for (auto &RC : RegClasses) {
2111- ++RCIdx;
21122110 if (!RC.Allocatable )
21132111 continue ;
21142112
@@ -2130,12 +2128,13 @@ void CodeGenRegBank::computeRegUnitSets() {
21302128 ++USIdx) {
21312129 if (isRegUnitSubSet (RCRegUnits, RegUnitSets[USIdx].Units )) {
21322130 LLVM_DEBUG (dbgs () << " " << USIdx);
2133- RegClassUnitSets[RCIdx ].push_back (USIdx);
2131+ RegClassUnitSets[RC. EnumValue ].push_back (USIdx);
21342132 }
21352133 }
21362134 LLVM_DEBUG (dbgs () << " \n " );
2137- assert ((!RegClassUnitSets[RCIdx].empty () || !RC.GeneratePressureSet ) &&
2138- " missing unit set for regclass" );
2135+ assert (
2136+ (!RegClassUnitSets[RC.EnumValue ].empty () || !RC.GeneratePressureSet ) &&
2137+ " missing unit set for regclass" );
21392138 }
21402139
21412140 // For each register unit, ensure that we have the list of UnitSets that
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