[AArch64][SME] Remove support for -arch64-enable-zpr-predicate-spills (#161819)

This was a stop-gap solution until we implemented
`-aarch64-split-sve-objects`. It was never enabled by default, and
likely saw no real-world use.

Let's remove this to reduce the maintenance burden.

Author: MacDue

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -2579,8 +2579,6 @@ unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
   case AArch64::STZ2Gi:
   case AArch64::STZGi:
   case AArch64::TAGPstack:
-  case AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO:
-  case AArch64::FILL_PPR_FROM_ZPR_SLOT_PSEUDO:
     return 2;
   case AArch64::LD1B_D_IMM:
   case AArch64::LD1B_H_IMM:
@@ -4387,8 +4385,6 @@ bool AArch64InstrInfo::getMemOpInfo(unsigned Opcode, TypeSize &Scale,
     MinOffset = -256;
     MaxOffset = 254;
     break;
-  case AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO:
-  case AArch64::FILL_PPR_FROM_ZPR_SLOT_PSEUDO:
   case AArch64::LDR_ZXI:
   case AArch64::STR_ZXI:
     Scale = TypeSize::getScalable(16);
@@ -5648,11 +5644,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
              "Unexpected register store without SVE store instructions");
       Opc = AArch64::STR_ZXI;
       StackID = TargetStackID::ScalableVector;
-    } else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
-      assert(Subtarget.isSVEorStreamingSVEAvailable() &&
-             "Unexpected predicate store without SVE store instructions");
-      Opc = AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO;
-      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 24:
@@ -5833,11 +5824,6 @@ void AArch64InstrInfo::loadRegFromStackSlot(
              "Unexpected register load without SVE load instructions");
       Opc = AArch64::LDR_ZXI;
       StackID = TargetStackID::ScalableVector;
-    } else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
-      assert(Subtarget.isSVEorStreamingSVEAvailable() &&
-             "Unexpected predicate load without SVE load instructions");
-      Opc = AArch64::FILL_PPR_FROM_ZPR_SLOT_PSEUDO;
-      StackID = TargetStackID::ScalableVector;
     }
     break;
   case 24:

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -57,10 +57,7 @@ static bool isPartOfZPRCalleeSaves(MachineBasicBlock::iterator I) {
   case AArch64::ST1B_2Z_IMM:
   case AArch64::STR_ZXI:
   case AArch64::LDR_ZXI:
-  case AArch64::CPY_ZPzI_B:
-  case AArch64::CMPNE_PPzZI_B:
   case AArch64::PTRUE_C_B:
-  case AArch64::PTRUE_B:
     return I->getFlag(MachineInstr::FrameSetup) ||
            I->getFlag(MachineInstr::FrameDestroy);
   case AArch64::SEH_SavePReg:

llvm/lib/Target/AArch64/AArch64PrologueEpilogue.cpp

@@ -980,19 +980,10 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
 //******************************************************************************
 
 // SVE predicate register classes.
-
-// Note: This hardware mode is enabled in AArch64Subtarget::getHwModeSet()
-// (without the use of the table-gen'd predicates).
-def SMEWithZPRPredicateSpills : HwMode<[Predicate<"false">]>;
-
-def PPRSpillFillRI : RegInfoByHwMode<
-      [DefaultMode,              SMEWithZPRPredicateSpills],
-      [RegInfo<16,16,16>,        RegInfo<16,128,128>]>;
-
 class PPRClass<int firstreg, int lastreg, int step = 1> : RegisterClass<"AArch64",
                                   [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16,
                                   (sequence "P%u", firstreg, lastreg, step)> {
-  let RegInfos = PPRSpillFillRI;
+  let Size = 16;
 }
 
 def PPR    : PPRClass<0, 15> {

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

@@ -86,11 +86,6 @@ static cl::alias AArch64StreamingStackHazardSize(
     cl::desc("alias for -aarch64-streaming-hazard-size"),
     cl::aliasopt(AArch64StreamingHazardSize));
 
-static cl::opt<bool> EnableZPRPredicateSpills(
-    "aarch64-enable-zpr-predicate-spills", cl::init(false), cl::Hidden,
-    cl::desc(
-        "Enables spilling/reloading SVE predicates as data vectors (ZPRs)"));
-
 static cl::opt<unsigned>
     VScaleForTuningOpt("sve-vscale-for-tuning", cl::Hidden,
                        cl::desc("Force a vscale for tuning factor for SVE"));
@@ -426,20 +421,6 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU,
   EnableSubregLiveness = EnableSubregLivenessTracking.getValue();
 }
 
-unsigned AArch64Subtarget::getHwModeSet() const {
-  AArch64HwModeBits Modes = AArch64HwModeBits::DefaultMode;
-
-  // Use a special hardware mode in streaming[-compatible] functions with
-  // aarch64-enable-zpr-predicate-spills. This changes the spill size (and
-  // alignment) for the predicate register class.
-  if (EnableZPRPredicateSpills.getValue() &&
-      (isStreaming() || isStreamingCompatible())) {
-    Modes |= AArch64HwModeBits::SMEWithZPRPredicateSpills;
-  }
-
-  return to_underlying(Modes);
-}
-
 const CallLowering *AArch64Subtarget::getCallLowering() const {
   return CallLoweringInfo.get();
 }

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

@@ -130,8 +130,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
                    bool IsStreaming = false, bool IsStreamingCompatible = false,
                    bool HasMinSize = false);
 
-  virtual unsigned getHwModeSet() const override;
-
 // Getters for SubtargetFeatures defined in tablegen
 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER)                    \
   bool GETTER() const { return ATTRIBUTE; }

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -58,20 +58,6 @@ def FORM_TRANSPOSED_REG_TUPLE_X4_PSEUDO :
   let hasSideEffects = 0;
 }
 
-def SPILL_PPR_TO_ZPR_SLOT_PSEUDO :
-  Pseudo<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), []>, Sched<[]>
-{
-  let mayStore = 1;
-  let hasSideEffects = 0;
-}
-
-def FILL_PPR_FROM_ZPR_SLOT_PSEUDO :
-  Pseudo<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), []>, Sched<[]>
-{
-  let mayLoad = 1;
-  let hasSideEffects = 0;
-}
-
 def SDTZALoadStore : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>]>;
 // SME ZA loads and stores
 def AArch64SMELdr : SDNode<"AArch64ISD::SME_ZA_LDR", SDTZALoadStore,