@@ -6129,7 +6129,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
61296129 .addImm(0);
61306130 }
61316131
6132- unsigned Opc = ( MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
6132+ unsigned Opc = MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO
61336133 ? AMDGPU::S_ADDC_U32
61346134 : AMDGPU::S_SUBB_U32;
61356135
@@ -16591,26 +16591,24 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1659116591 sd_match(LHS, m_Sub(m_Specific(RHS), m_Value()))) ||
1659216592 (CC == ISD::SETEQ && CRHS && CRHS->isZero() &&
1659316593 sd_match(LHS, m_Add(m_Value(), m_One()))))) {
16594- EVT TargetType = MVT::i32;
16595- EVT CarryVT = MVT::i1;
1659616594 bool IsAdd = LHS.getOpcode() == ISD::ADD;
1659716595
1659816596 SDValue Op0 = LHS.getOperand(0);
1659916597 SDValue Op1 = LHS.getOperand(1);
1660016598
16601- SDValue Op0Lo = DAG.getNode(ISD::TRUNCATE, SL, TargetType , Op0);
16602- SDValue Op1Lo = DAG.getNode(ISD::TRUNCATE, SL, TargetType , Op1);
16599+ SDValue Op0Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32 , Op0);
16600+ SDValue Op1Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32 , Op1);
1660316601
1660416602 SDValue Op0Hi = getHiHalf64(Op0, DAG);
1660516603 SDValue Op1Hi = getHiHalf64(Op1, DAG);
1660616604
1660716605 SDValue NodeLo =
1660816606 DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, SL,
16609- DAG.getVTList(TargetType, CarryVT ), {Op0Lo, Op1Lo});
16607+ DAG.getVTList(MVT::i32, MVT::i1 ), {Op0Lo, Op1Lo});
1661016608
1661116609 SDValue CarryInHi = NodeLo.getValue(1);
1661216610 SDValue NodeHi = DAG.getNode(IsAdd ? ISD::UADDO_CARRY : ISD::USUBO_CARRY,
16613- SL, DAG.getVTList(TargetType, CarryVT ),
16611+ SL, DAG.getVTList(MVT::i32, MVT::i1 ),
1661416612 {Op0Hi, Op1Hi, CarryInHi});
1661516613
1661616614 SDValue ResultLo = NodeLo.getValue(0);
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