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[llvm][CodeGen] Fix the issue caused by live interval checking in window scheduler (#123184)
At some corner cases, the cloned MI still retains an old slot index, which leads to the compiler crashing. This patch update the slot index map before delete the recycled MI. #123165
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8 files changed

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-9
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8 files changed

+99
-9
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -810,7 +810,7 @@ class TargetInstrInfo : public MCInstrInfo {
810810
///
811811
/// Once this function is called, no other functions on this object are
812812
/// valid; the loop has been removed.
813-
virtual void disposed() = 0;
813+
virtual void disposed(LiveIntervals *LIS = nullptr) {}
814814

815815
/// Return true if the target can expand pipelined schedule with modulo
816816
/// variable expansion.

‎llvm/lib/CodeGen/ModuloSchedule.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -899,7 +899,7 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
899899
LastEpi->eraseFromParent();
900900
}
901901
if (LastPro == KernelBB) {
902-
LoopInfo->disposed();
902+
LoopInfo->disposed(&LIS);
903903
NewKernel = nullptr;
904904
}
905905
LastPro->clear();

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10143,7 +10143,6 @@ class AArch64PipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
1014310143

1014410144
void adjustTripCount(int TripCountAdjust) override {}
1014510145

10146-
void disposed() override {}
1014710146
bool isMVEExpanderSupported() override { return true; }
1014810147
};
1014910148
} // namespace

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6850,8 +6850,6 @@ class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
68506850
void setPreheader(MachineBasicBlock *NewPreheader) override {}
68516851

68526852
void adjustTripCount(int TripCountAdjust) override {}
6853-
6854-
void disposed() override {}
68556853
};
68566854

68576855
void ARMPipelinerLoopInfo::bumpCrossIterationPressure(RegPressureTracker &RPT,

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "llvm/ADT/StringExtras.h"
2222
#include "llvm/ADT/StringRef.h"
2323
#include "llvm/CodeGen/DFAPacketizer.h"
24+
#include "llvm/CodeGen/LiveIntervals.h"
2425
#include "llvm/CodeGen/LivePhysRegs.h"
2526
#include "llvm/CodeGen/MachineBasicBlock.h"
2627
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
@@ -795,7 +796,11 @@ class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
795796
Loop->getOperand(1).setReg(NewLoopCount);
796797
}
797798

798-
void disposed() override { Loop->eraseFromParent(); }
799+
void disposed(LiveIntervals *LIS) override {
800+
if (LIS)
801+
LIS->RemoveMachineInstrFromMaps(*Loop);
802+
Loop->eraseFromParent();
803+
}
799804
};
800805
} // namespace
801806

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5693,7 +5693,11 @@ class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
56935693
// so we don't need to generate any thing here.
56945694
}
56955695

5696-
void disposed() override {
5696+
void disposed(LiveIntervals *LIS) override {
5697+
if (LIS) {
5698+
LIS->RemoveMachineInstrFromMaps(*Loop);
5699+
LIS->RemoveMachineInstrFromMaps(*LoopCount);
5700+
}
56975701
Loop->eraseFromParent();
56985702
// Ensure the loop setup instruction is deleted too.
56995703
LoopCount->eraseFromParent();

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4277,8 +4277,6 @@ class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
42774277
void setPreheader(MachineBasicBlock *NewPreheader) override {}
42784278

42794279
void adjustTripCount(int TripCountAdjust) override {}
4280-
4281-
void disposed() override {}
42824280
};
42834281
} // namespace
42844282

‎llvm/test/CodeGen/Hexagon/swp-ws-live-intervals-issue123165.mir‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -o -| FileCheck %s
3+
4+
...
5+
---
6+
name: test_swp_ws_live_intervals
7+
tracksRegLiveness: true
8+
body: |
9+
; CHECK-LABEL: name: test_swp_ws_live_intervals
10+
; CHECK: bb.0:
11+
; CHECK-NEXT: successors: %bb.1(0x80000000)
12+
; CHECK-NEXT: liveins: $r0
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:intregs = COPY $r0
15+
; CHECK-NEXT: J2_loop0i %bb.1, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
16+
; CHECK-NEXT: {{ $}}
17+
; CHECK-NEXT: bb.1:
18+
; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
19+
; CHECK-NEXT: {{ $}}
20+
; CHECK-NEXT: [[L2_loadri_io:%[0-9]+]]:intregs = L2_loadri_io [[COPY]], 0
21+
; CHECK-NEXT: [[L2_loadrub_io:%[0-9]+]]:intregs = L2_loadrub_io [[L2_loadri_io]], 0
22+
; CHECK-NEXT: [[PS_loadriabs:%[0-9]+]]:intregs = PS_loadriabs 0
23+
; CHECK-NEXT: S2_storerb_io [[PS_loadriabs]], 0, [[L2_loadrub_io]]
24+
; CHECK-NEXT: ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
25+
; CHECK-NEXT: {{ $}}
26+
; CHECK-NEXT: bb.2:
27+
; CHECK-NEXT: successors: %bb.5(0x80000000)
28+
; CHECK-NEXT: {{ $}}
29+
; CHECK-NEXT: [[A2_tfrsi:%[0-9]+]]:intregs = A2_tfrsi 0
30+
; CHECK-NEXT: [[A2_tfrsi1:%[0-9]+]]:intregs = A2_tfrsi -1
31+
; CHECK-NEXT: J2_jump %bb.5, implicit-def $pc
32+
; CHECK-NEXT: {{ $}}
33+
; CHECK-NEXT: bb.3:
34+
; CHECK-NEXT: S2_storeri_io [[COPY]], 0, %18
35+
; CHECK-NEXT: PS_jmpret $r31, implicit-def dead $pc
36+
; CHECK-NEXT: {{ $}}
37+
; CHECK-NEXT: bb.5:
38+
; CHECK-NEXT: successors: %bb.7(0x80000000)
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: [[A2_addi:%[0-9]+]]:intregs = A2_addi [[A2_tfrsi1]], 1
41+
; CHECK-NEXT: J2_jump %bb.7, implicit-def $pc
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: bb.7:
44+
; CHECK-NEXT: successors: %bb.3(0x80000000)
45+
; CHECK-NEXT: {{ $}}
46+
; CHECK-NEXT: [[PHI:%[0-9]+]]:intregs = PHI [[A2_tfrsi]], %bb.5
47+
; CHECK-NEXT: J2_jump %bb.3, implicit-def $pc
48+
bb.0:
49+
successors: %bb.1(0x80000000)
50+
liveins: $r0
51+
52+
%0:intregs = COPY $r0
53+
J2_loop0i %bb.1, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
54+
55+
bb.1:
56+
successors: %bb.2(0x04000000), %bb.1(0x7c000000)
57+
58+
%1:intregs = L2_loadri_io %0, 0
59+
%2:intregs = L2_loadrub_io killed %1, 0
60+
%3:intregs = PS_loadriabs 0
61+
S2_storerb_io killed %3, 0, killed %2
62+
ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
63+
64+
bb.2:
65+
successors: %bb.4(0x80000000)
66+
67+
%4:intregs = A2_tfrsi 0
68+
%5:intregs = A2_tfrsi -1
69+
J2_loop0i %bb.4, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
70+
J2_jump %bb.4, implicit-def $pc
71+
72+
bb.3:
73+
S2_storeri_io %0, 0, %6
74+
PS_jmpret $r31, implicit-def dead $pc
75+
76+
bb.4:
77+
successors: %bb.3(0x04000000), %bb.4(0x7c000000)
78+
79+
%7:intregs = PHI %5, %bb.2, %8, %bb.4
80+
%6:intregs = PHI %4, %bb.2, %9, %bb.4
81+
%8:intregs = A2_addi %7, 1
82+
%9:intregs = S2_setbit_i %8, 0
83+
ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
84+
J2_jump %bb.3, implicit-def $pc
85+
86+
...

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