fixup! Add MIR test

Author: mshockwave

llvm/test/CodeGen/RISCV/postra-copy-expand.mir

@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=postrapseudos %s -o - | FileCheck %s
+
+---
+name:            copy
+isSSA:           false
+noVRegs:         true
+liveins:
+  - { reg: '$v0', virtual-reg: '' }
+body:             |
+  bb.0:
+    liveins: $v0
+
+    ; CHECK-LABEL: name: copy
+    ; CHECK: liveins: $v0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v24 = VMV1R_V $v18, implicit $vtype, implicit $v14_v15_v16_v17_v18, implicit $vtype
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    renamable $v20_v21_v22_v23_v24 = COPY renamable $v14_v15_v16_v17_v18, implicit $vtype
+    PseudoRET implicit $v0
+
+...