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1 parent a6cb0ce commit aaa2b58Copy full SHA for aaa2b58
llvm/docs/LangRef.rst
@@ -24125,9 +24125,9 @@ This is an overloaded intrinsic.
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Overview:
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"""""""""
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-Given a scalar load from %ptrA, followed by a scalar store to %ptrB, this
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-instruction generates a mask where an active lane indicates that there is no
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-write-after-read hazard for this lane.
+Given a vector load from %ptrA, followed by a vector store to %ptrB, this
+intrinsic generates a mask where a true lane indicates that the accesses don't
+overlap for that lane.
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A write-after-read hazard occurs when a write-after-read sequence for a given
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lane in a vector ends up being executed as a read-after-write sequence due to
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