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[AArch64] Add assembly/disassembly for zeroing SVE2 integer instructions
This patch adds assembly/disassembly for the following SVE2.2 instructions - SQABS (zeroing) - SQNEG (zeroing) - URECPE (zeroing) - USQRTE (zeroing) - Refactor the existing merging forms to remove the now redundant bit 17 argument. - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
1 parent 47c1abf commit ab04996

15 files changed

+372
-22
lines changed

‎llvm/lib/Target/AArch64/AArch64.td‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,13 @@ def SVEUnsupported : AArch64Unsupported {
7373
SVE2Unsupported.F);
7474
}
7575

76-
let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1, HasSVE2p1orSSVE_AES] in
77-
def SME2p1Unsupported : AArch64Unsupported;
76+
let F = [HasSME2p2, HasSVE2p2orSME2p2] in
77+
def SME2p2Unsupported : AArch64Unsupported;
78+
79+
def SME2p1Unsupported : AArch64Unsupported {
80+
let F = !listconcat([HasSME2p1, HasSVE2p1_or_HasSME2p1, HasSVE2p1orSSVE_AES],
81+
SME2p2Unsupported.F);
82+
}
7883

7984
def SME2Unsupported : AArch64Unsupported {
8085
let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA,

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3586,10 +3586,10 @@ let Predicates = [HasSVE2orSME] in {
35863586
defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp", int_aarch64_sve_uminp>;
35873587

35883588
// SVE2 integer unary operations (predicated)
3589-
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe", int_aarch64_sve_urecpe>;
3590-
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte", int_aarch64_sve_ursqrte>;
3591-
defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs", int_aarch64_sve_sqabs>;
3592-
defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg", int_aarch64_sve_sqneg>;
3589+
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b00, "urecpe", int_aarch64_sve_urecpe>;
3590+
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b01, "ursqrte", int_aarch64_sve_ursqrte>;
3591+
defm SQABS_ZPmZ : sve2_int_un_pred_arit< 0b10, "sqabs", int_aarch64_sve_sqabs>;
3592+
defm SQNEG_ZPmZ : sve2_int_un_pred_arit< 0b11, "sqneg", int_aarch64_sve_sqneg>;
35933593

35943594
// SVE2 saturating add/subtract
35953595
defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd", int_aarch64_sve_sqadd>;
@@ -4226,6 +4226,11 @@ let Predicates = [HasSVE2p2orSME2p2] in {
42264226

42274227
// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
42284228
def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
4229+
4230+
def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;
4231+
def URSQRTE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b01, "ursqrte", ZPR32>;
4232+
defm SQABS_ZPzZ : sve2_int_un_pred_arit_z<0b10, "sqabs">;
4233+
defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z<0b11, "sqneg">;
42294234
} // End HasSME2p2orSVE2p2
42304235

42314236
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 40 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3895,7 +3895,7 @@ multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm, SDPatternOperato
38953895
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv4i32, !cast<Instruction>(NAME # _D)>;
38963896
}
38973897

3898-
class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
3898+
class sve2_int_un_pred_arit<bits<2> sz, bits<2> opc,
38993899
string asm, ZPRRegOp zprty>
39003900
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
39013901
asm, "\t$Zd, $Pg/m, $Zn",
@@ -3907,23 +3907,44 @@ class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
39073907
let Inst{31-24} = 0b01000100;
39083908
let Inst{23-22} = sz;
39093909
let Inst{21-20} = 0b00;
3910-
let Inst{19} = Q;
3911-
let Inst{18} = 0b0;
3912-
let Inst{17-16} = opc;
3910+
let Inst{19} = opc{1};
3911+
let Inst{18-17} = 0b00;
3912+
let Inst{16} = opc{0};
39133913
let Inst{15-13} = 0b101;
39143914
let Inst{12-10} = Pg;
39153915
let Inst{9-5} = Zn;
39163916
let Inst{4-0} = Zd;
3917-
39183917
let Constraints = "$Zd = $_Zd";
39193918
let DestructiveInstType = DestructiveUnaryPassthru;
39203919
let ElementSize = zprty.ElementSize;
39213920
let hasSideEffects = 0;
39223921
}
39233922

3924-
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
3923+
class sve2_int_un_pred_arit_z<bits<2> sz, bits<2> opc,
3924+
string asm, ZPRRegOp zprty>
3925+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
3926+
asm, "\t$Zd, $Pg/z, $Zn",
3927+
"",
3928+
[]>, Sched<[]> {
3929+
bits<3> Pg;
3930+
bits<5> Zd;
3931+
bits<5> Zn;
3932+
let Inst{31-24} = 0b01000100;
3933+
let Inst{23-22} = sz;
3934+
let Inst{21-20} = 0b00;
3935+
let Inst{19} = opc{1};
3936+
let Inst{18-17} = 0b01;
3937+
let Inst{16} = opc{0};
3938+
let Inst{15-13} = 0b101;
3939+
let Inst{12-10} = Pg;
3940+
let Inst{9-5} = Zn;
3941+
let Inst{4-0} = Zd;
3942+
let hasSideEffects = 0;
3943+
}
3944+
3945+
multiclass sve2_int_un_pred_arit_s<bits<2> opc, string asm,
39253946
SDPatternOperator op> {
3926-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3947+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
39273948
SVEPseudo2Instr<NAME # _S, 1>;
39283949

39293950
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
@@ -3933,14 +3954,14 @@ multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
39333954
defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
39343955
}
39353956

3936-
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op> {
3937-
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>,
3957+
multiclass sve2_int_un_pred_arit<bits<2> opc, string asm, SDPatternOperator op> {
3958+
def _B : sve2_int_un_pred_arit<0b00, opc, asm, ZPR8>,
39383959
SVEPseudo2Instr<NAME # _B, 1>;
3939-
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>,
3960+
def _H : sve2_int_un_pred_arit<0b01, opc, asm, ZPR16>,
39403961
SVEPseudo2Instr<NAME # _H, 1>;
3941-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3962+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
39423963
SVEPseudo2Instr<NAME # _S, 1>;
3943-
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>,
3964+
def _D : sve2_int_un_pred_arit<0b11, opc, asm, ZPR64>,
39443965
SVEPseudo2Instr<NAME # _D, 1>;
39453966

39463967
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
@@ -3959,6 +3980,13 @@ multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op>
39593980
defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
39603981
}
39613982

3983+
multiclass sve2_int_un_pred_arit_z<bits<2> opc, string asm> {
3984+
def _B : sve2_int_un_pred_arit_z<0b00, opc, asm, ZPR8>;
3985+
def _H : sve2_int_un_pred_arit_z<0b01, opc, asm, ZPR16>;
3986+
def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>;
3987+
def _D : sve2_int_un_pred_arit_z<0b11, opc, asm, ZPR64>;
3988+
}
3989+
39623990
//===----------------------------------------------------------------------===//
39633991
// SVE2 Widening Integer Arithmetic Group
39643992
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqabs z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqabs z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqneg z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqneg z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
urecpe z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: urecpe z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
ursqrte z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: ursqrte z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2p2/sqabs_z-diagnostics.s‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid element width
5+
6+
sqabs z31.b, p7/z, z31.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: sqabs z31.b, p7/z, z31.h
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
sqabs z31.d, p7/z, z31.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: sqabs z31.d, p7/z, z31.s
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// ------------------------------------------------------------------------- //
17+
// Invalid predicate
18+
19+
sqabs z31.b, p8/z, z31.b
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
21+
// CHECK-NEXT: sqabs z31.b, p8/z, z31.b
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
// --------------------------------------------------------------------------//
25+
// Negative tests for instructions that are incompatible with movprfx
26+
27+
movprfx z0.h, p0/z, z7.h
28+
sqabs z0.h, p0/z, z3.h
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
30+
// CHECK-NEXT: sqabs z0.h, p0/z, z3.h
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
movprfx z0, z7
34+
sqabs z0.h, p0/z, z3.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
36+
// CHECK-NEXT: sqabs z0.h, p0/z, z3.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/sqabs_z.s‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
sqabs z0.b, p0/z, z0.b // 01000100-00001010-10100000-00000000
18+
// CHECK-INST: sqabs z0.b, p0/z, z0.b
19+
// CHECK-ENCODING: [0x00,0xa0,0x0a,0x44]
20+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
21+
// CHECK-UNKNOWN: 440aa000 <unknown>
22+
23+
sqabs z21.h, p5/z, z10.h // 01000100-01001010-10110101-01010101
24+
// CHECK-INST: sqabs z21.h, p5/z, z10.h
25+
// CHECK-ENCODING: [0x55,0xb5,0x4a,0x44]
26+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
27+
// CHECK-UNKNOWN: 444ab555 <unknown>
28+
29+
sqabs z23.s, p3/z, z13.s // 01000100-10001010-10101101-10110111
30+
// CHECK-INST: sqabs z23.s, p3/z, z13.s
31+
// CHECK-ENCODING: [0xb7,0xad,0x8a,0x44]
32+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
33+
// CHECK-UNKNOWN: 448aadb7 <unknown>
34+
35+
sqabs z31.d, p7/z, z31.d // 01000100-11001010-10111111-11111111
36+
// CHECK-INST: sqabs z31.d, p7/z, z31.d
37+
// CHECK-ENCODING: [0xff,0xbf,0xca,0x44]
38+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
39+
// CHECK-UNKNOWN: 44cabfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/sqneg_z-diagnostics.s‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// ------------------------------------------------------------------------- //
4+
// Invalid element width
5+
6+
sqneg z31.b, p7/z, z31.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: sqneg z31.b, p7/z, z31.h
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
sqneg z31.d, p7/z, z31.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: sqneg z31.d, p7/z, z31.s
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// ------------------------------------------------------------------------- //
17+
// Invalid predicate
18+
19+
sqneg z31.b, p8/z, z31.b
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
21+
// CHECK-NEXT: sqneg z31.b, p8/z, z31.b
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
// --------------------------------------------------------------------------//
25+
// Negative tests for instructions that are incompatible with movprfx
26+
27+
movprfx z0.h, p0/z, z7.h
28+
sqneg z0.h, p0/z, z3.h
29+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
30+
// CHECK-NEXT: sqneg z0.h, p0/z, z3.h
31+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
32+
33+
movprfx z0, z7
34+
sqneg z0.h, p0/z, z3.h
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
36+
// CHECK-NEXT: sqneg z0.h, p0/z, z3.h
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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