[AVR] Refactor MUL/FMUL instruction descriptions (NFC) (#156862)

* Split MULSU format from MULS and fix the comment
* Remove custom decoder functions for the instructions
* Add a decoder for LD8lo register class

Author: s-barannikov

llvm/lib/Target/AVR/AVRInstrFormats.td

@@ -228,22 +228,37 @@ class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
 }
 
 //===----------------------------------------------------------------------===//
-// MULSrr special encoding: <|0000|0010|dddd|rrrr|>
+// MULS special encoding: <|0000|0010|dddd|rrrr|>
 // d = multiplicand = 4 bits
 // r = multiplier = 4 bits
 // (Only accepts r16-r31)
 //===----------------------------------------------------------------------===//
-class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
+class FMULSRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
     : AVRInst16<outs, ins, asmstr, pattern> {
-  bits<5> rd; // accept 5 bits but only encode the lower 4
-  bits<5> rr; // accept 5 bits but only encode the lower 4
+  bits<4> rd;
+  bits<4> rr;
 
-  let Inst{15 - 9} = 0b0000001;
-  let Inst{8} = f;
-  let Inst{7 - 4} = rd{3 - 0};
-  let Inst{3 - 0} = rr{3 - 0};
+  let Inst{15 - 8} = 0b00000010;
+  let Inst{7 - 4} = rd;
+  let Inst{3 - 0} = rr;
+}
+
+//===----------------------------------------------------------------------===//
+// MULSU special encoding: <|0000|0011|0ddd|0rrr|>
+// d = multiplicand = 3 bits
+// r = multiplier = 3 bits
+// (Only accepts r16-r23)
+//===----------------------------------------------------------------------===//
+class FMULSURdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
+    : AVRInst16<outs, ins, asmstr, pattern> {
+  bits<3> rd;
+  bits<3> rr;
 
-  let DecoderMethod = "decodeFMUL2RdRr";
+  let Inst{15 - 8} = 0b00000011;
+  let Inst{7} = 0;
+  let Inst{6 - 4} = rd;
+  let Inst{3} = 0;
+  let Inst{2 - 0} = rr;
 }
 
 // Special encoding for the FMUL family of instructions.
@@ -266,8 +281,6 @@ class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{6 - 4} = rd;
   let Inst{3} = f{0};
   let Inst{2 - 0} = rr;
-
-  let DecoderMethod = "decodeFFMULRdRr";
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/AVR/AVRInstrInfo.td

@@ -495,13 +495,13 @@ let isCommutable = 1, Defs = [R1, R0, SREG] in {
                         "mul\t$rd, $rr", []>,
                   Requires<[SupportsMultiplication]>;
 
-    def MULSRdRr : FMUL2RdRr<0, (outs), (ins LD8:$rd, LD8:$rr),
+    def MULSRdRr : FMULSRdRr<(outs), (ins LD8:$rd, LD8:$rr),
                              "muls\t$rd, $rr", []>,
                    Requires<[SupportsMultiplication]>;
   }
 
-  def MULSURdRr : FMUL2RdRr<1, (outs), (ins LD8lo:$rd, LD8lo:$rr),
-                            "mulsu\t$rd, $rr", []>,
+  def MULSURdRr : FMULSURdRr<(outs), (ins LD8lo:$rd, LD8lo:$rr),
+                             "mulsu\t$rd, $rr", []>,
                   Requires<[SupportsMultiplication]>;
 
   def FMUL : FFMULRdRr<0b01, (outs), (ins LD8lo:$rd, LD8lo:$rr),

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

@@ -83,11 +83,18 @@ static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder) {
-  if (RegNo > 15)
-    return MCDisassembler::Fail;
+  assert(isUInt<4>(RegNo));
+  // Only r16...r31 are legal.
+  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[16 + RegNo]));
+  return MCDisassembler::Success;
+}
 
-  unsigned Register = GPRDecoderTable[RegNo + 16];
-  Inst.addOperand(MCOperand::createReg(Register));
+static DecodeStatus DecodeLD8loRegisterClass(MCInst &Inst, unsigned RegNo,
+                                             uint64_t Address,
+                                             const MCDisassembler *Decoder) {
+  assert(isUInt<3>(RegNo));
+  // Only r16...r23 are legal.
+  Inst.addOperand(MCOperand::createReg(GPRDecoderTable[16 + RegNo]));
   return MCDisassembler::Success;
 }
 
@@ -122,20 +129,6 @@ static DecodeStatus decodeRelCondBrTarget13(MCInst &Inst, unsigned Field,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address,
-                                    const MCDisassembler *Decoder) {
-  unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
-  unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
-  if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
-      MCDisassembler::Fail)
-    return MCDisassembler::Fail;
-  if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
-      MCDisassembler::Fail)
-    return MCDisassembler::Fail;
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
                                     uint64_t Address,
                                     const MCDisassembler *Decoder) {
@@ -166,20 +159,6 @@ static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
   return MCDisassembler::Success;
 }
 
-static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
-                                    uint64_t Address,
-                                    const MCDisassembler *Decoder) {
-  unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
-  unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
-  if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
-      MCDisassembler::Fail)
-    return MCDisassembler::Fail;
-  if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
-      MCDisassembler::Fail)
-    return MCDisassembler::Fail;
-  return MCDisassembler::Success;
-}
-
 static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
                                 const MCDisassembler *Decoder) {
   // As in the EncoderMethod `AVRMCCodeEmitter::encodeMemri`, the memory