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1 parent 1463da8 commit ab27127Copy full SHA for ab27127
llvm/test/CodeGen/RISCV/and-shl.ll
@@ -77,3 +77,22 @@ define i32 @and_0xfff_shl_2_multi_use(i32 %x) {
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%r = add i32 %a, %s
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ret i32 %r
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}
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+
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+define i64 @and_0xfff_shl_33(i64 %x) {
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+; RV32I-LABEL: and_0xfff_shl_33:
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+; RV32I: # %bb.0:
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+; RV32I-NEXT: slli a0, a0, 20
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+; RV32I-NEXT: srli a1, a0, 19
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+; RV32I-NEXT: li a0, 0
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+; RV32I-NEXT: ret
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+;
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+; RV64I-LABEL: and_0xfff_shl_33:
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+; RV64I: # %bb.0:
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+; RV64I-NEXT: slli a0, a0, 52
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+; RV64I-NEXT: srli a0, a0, 52
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+; RV64I-NEXT: slli a0, a0, 33
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+; RV64I-NEXT: ret
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+ %a = and i64 %x, 4095
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+ %s = shl i64 %a, 33
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+ ret i64 %s
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+}
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