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[mlir][py] Make Python enum gen consistent with C++ type
In C++ generation we take the main file as the one for which we are generating methods for. E.g., mlir-tblgen -gen-type-constraint-decls Foo.td generates decls for Foo.td rather than anything transitively included. It makes what is acted upon more explicit. Unfortunately enums didn't get the same attention. So one would generate for enums even where files included others. Python side there is an added layer of indirection which is not needed here. Pass the enum file to be generated directly to the tool and filter on main file to avoid special casing. Now if there were multiple files with enums (instead of common case 1), one would have to invoke the command multiple times and include all. That is less painful Python side than C++ side (given the common import all in the wrapper dialect.py file). Note: this is just a partial example for discussion.
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mlir/include/mlir/Dialect/GPU/IR/GPUBase.td

Lines changed: 164 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,170 @@ def GPU_AddressSpaceEnum : GPU_I32Enum<
9999
def GPU_AddressSpaceAttr :
100100
GPU_I32EnumAttr<"address_space", GPU_AddressSpaceEnum>;
101101

102+
def GPU_Dimension : I32EnumAttr<"Dimension",
103+
"a dimension, either 'x', 'y', or 'z'",
104+
[
105+
I32EnumAttrCase<"x", 0>,
106+
I32EnumAttrCase<"y", 1>,
107+
I32EnumAttrCase<"z", 2>
108+
]>{
109+
let genSpecializedAttr = 0;
110+
let cppNamespace = "::mlir::gpu";
111+
}
112+
def GPU_DimensionAttr : EnumAttr<GPU_Dialect, GPU_Dimension, "dim">;
113+
114+
// These mirror the reduction combining kinds from the vector dialect.
115+
def GPU_AllReduceOpAdd : I32EnumAttrCase<"ADD", 0, "add">;
116+
def GPU_AllReduceOpMul : I32EnumAttrCase<"MUL", 1, "mul">;
117+
def GPU_AllReduceOpMinUI : I32EnumAttrCase<"MINUI", 2, "minui">;
118+
def GPU_AllReduceOpMinSI : I32EnumAttrCase<"MINSI", 3, "minsi">;
119+
// Follows the `arith.minnumf` semantics.
120+
def GPU_AllReduceOpMinnumF : I32EnumAttrCase<"MINNUMF", 4, "minnumf">;
121+
def GPU_AllReduceOpMaxUI : I32EnumAttrCase<"MAXUI", 5, "maxui">;
122+
def GPU_AllReduceOpMaxSI : I32EnumAttrCase<"MAXSI", 6, "maxsi">;
123+
// Follows the `arith.maxnumf` semantics.
124+
def GPU_AllReduceOpMaxnumF : I32EnumAttrCase<"MAXNUMF", 7, "maxnumf">;
125+
def GPU_AllReduceOpAnd : I32EnumAttrCase<"AND", 8, "and">;
126+
def GPU_AllReduceOpOr : I32EnumAttrCase<"OR", 9, "or">;
127+
def GPU_AllReduceOpXor : I32EnumAttrCase<"XOR", 10, "xor">;
128+
// Follows the `arith.minimumf` semantics.
129+
def GPU_AllReduceOpMinimumF : I32EnumAttrCase<"MINIMUMF", 11, "minimumf">;
130+
// Follows the `arith.maximumf` semantics.
131+
def GPU_AllReduceOpMaximumF : I32EnumAttrCase<"MAXIMUMF", 12, "maximumf">;
132+
133+
def GPU_AllReduceOperation : I32EnumAttr<"AllReduceOperation",
134+
"built-in reduction operations supported by gpu.allreduce.",
135+
[
136+
GPU_AllReduceOpAdd,
137+
GPU_AllReduceOpMul,
138+
GPU_AllReduceOpMinUI,
139+
GPU_AllReduceOpMinSI,
140+
GPU_AllReduceOpMinnumF,
141+
GPU_AllReduceOpMaxUI,
142+
GPU_AllReduceOpMaxSI,
143+
GPU_AllReduceOpMaxnumF,
144+
GPU_AllReduceOpAnd,
145+
GPU_AllReduceOpOr,
146+
GPU_AllReduceOpXor,
147+
GPU_AllReduceOpMinimumF,
148+
GPU_AllReduceOpMaximumF
149+
]>{
150+
let genSpecializedAttr = 0;
151+
let cppNamespace = "::mlir::gpu";
152+
}
153+
def GPU_AllReduceOperationAttr : EnumAttr<GPU_Dialect, GPU_AllReduceOperation,
154+
"all_reduce_op">;
155+
156+
def GPU_ShuffleOpXor : I32EnumAttrCase<"XOR", 0, "xor">;
157+
def GPU_ShuffleOpDown : I32EnumAttrCase<"DOWN", 1, "down">;
158+
def GPU_ShuffleOpUp : I32EnumAttrCase<"UP", 2, "up">;
159+
def GPU_ShuffleOpIdx : I32EnumAttrCase<"IDX", 3, "idx">;
160+
161+
def GPU_ShuffleMode : I32EnumAttr<"ShuffleMode",
162+
"Indexing modes supported by gpu.shuffle.",
163+
[
164+
GPU_ShuffleOpXor, GPU_ShuffleOpUp, GPU_ShuffleOpDown, GPU_ShuffleOpIdx,
165+
]> {
166+
let genSpecializedAttr = 0;
167+
let cppNamespace = "::mlir::gpu";
168+
}
169+
def GPU_ShuffleModeAttr : EnumAttr<GPU_Dialect, GPU_ShuffleMode,
170+
"shuffle_mode">;
171+
172+
def GPU_ElementwiseOpAddF : I32EnumAttrCase<"ADDF", 0, "addf">;
173+
def GPU_ElementwiseOpMulF : I32EnumAttrCase<"MULF", 1, "mulf">;
174+
def GPU_ElementwiseOpSUBF : I32EnumAttrCase<"SUBF", 2, "subf">;
175+
def GPU_ElementwiseOpMaxF : I32EnumAttrCase<"MAXF", 3, "maxf">;
176+
def GPU_ElementwiseOpMinF : I32EnumAttrCase<"MINF", 4, "minf">;
177+
def GPU_ElementwiseOpDivF : I32EnumAttrCase<"DIVF", 5, "divf">;
178+
def GPU_ElementwiseOpAddI : I32EnumAttrCase<"ADDI", 6, "addi">;
179+
def GPU_ElementwiseOpMulI : I32EnumAttrCase<"MULI", 7, "muli">;
180+
def GPU_ElementwiseOpSUBI : I32EnumAttrCase<"SUBI", 8, "subi">;
181+
def GPU_ElementwiseOpDivS : I32EnumAttrCase<"DIVS", 9, "divs">;
182+
def GPU_ElementwiseOpDivU : I32EnumAttrCase<"DIVU", 10, "divu">;
183+
def GPU_ElementwiseOpNEGF : I32EnumAttrCase<"NEGATEF", 11, "negatef">;
184+
def GPU_ElementwiseOpNEGS : I32EnumAttrCase<"NEGATES", 12, "negates">;
185+
def GPU_ElementwiseOpEXTF : I32EnumAttrCase<"EXTF", 13, "extf">;
186+
187+
def MMAElementWise : I32EnumAttr<"MMAElementwiseOp",
188+
"elementwise operation to apply to mma matrix", [
189+
GPU_ElementwiseOpAddF,
190+
GPU_ElementwiseOpMulF,
191+
GPU_ElementwiseOpSUBF,
192+
GPU_ElementwiseOpMaxF,
193+
GPU_ElementwiseOpMinF,
194+
GPU_ElementwiseOpDivF,
195+
GPU_ElementwiseOpAddI,
196+
GPU_ElementwiseOpMulI,
197+
GPU_ElementwiseOpSUBI,
198+
GPU_ElementwiseOpDivS,
199+
GPU_ElementwiseOpDivU,
200+
GPU_ElementwiseOpNEGF,
201+
GPU_ElementwiseOpNEGS,
202+
GPU_ElementwiseOpEXTF
203+
]> {
204+
let genSpecializedAttr = 0;
205+
let cppNamespace = "::mlir::gpu";
206+
}
207+
def MMAElementWiseAttr : EnumAttr<GPU_Dialect, MMAElementWise,
208+
"mma_element_wise">;
209+
210+
def GPU_Prune2To4SpMatFlag : I32EnumAttr<"Prune2To4SpMatFlag",
211+
"pruning strategy for 2:4 sparse matrix",
212+
[
213+
I32EnumAttrCase<"NONE", 0>,
214+
I32EnumAttrCase<"PRUNE_ONLY", 1>,
215+
I32EnumAttrCase<"PRUNE_AND_CHECK", 2>,
216+
]> {
217+
let genSpecializedAttr = 0;
218+
let cppNamespace = GPU_Dialect.cppNamespace;
219+
}
220+
221+
def GPU_Prune2To4SpMatFlagAttr : EnumAttr<GPU_Dialect, GPU_Prune2To4SpMatFlag,
222+
"prune_2to4_spmat_flag">{
223+
let defaultValue = "Prune2To4SpMatFlag::PRUNE_AND_CHECK";
224+
}
225+
226+
// To avoid coupling this dialect with cusparse.h specifics, we hardcoded magic
227+
// literals in this enum. Note that this should be kept in sync with
228+
// cusparseOperation_t in cusparse.h:
229+
// typedef enum {
230+
// CUSPARSE_OPERATION_NON_TRANSPOSE = 0,
231+
// CUSPARSE_OPERATION_TRANSPOSE = 1,
232+
// CUSPARSE_OPERATION_CONJUGATE_TRANSPOSE = 2
233+
// } cusparseOperation_t;
234+
// TODO: find a proper way to keep them in sync?
235+
def GPU_TransposeMode : I32EnumAttr<"TransposeMode",
236+
"transpose mode of sparse matrix supported by sparse tensor ops",
237+
[
238+
I32EnumAttrCase<"NON_TRANSPOSE", 0>,
239+
I32EnumAttrCase<"TRANSPOSE", 1>,
240+
I32EnumAttrCase<"CONJUGATE_TRANSPOSE", 2>,
241+
]> {
242+
let genSpecializedAttr = 0;
243+
let cppNamespace = GPU_Dialect.cppNamespace;
244+
}
245+
246+
def GPU_TransposeModeAttr : EnumAttr<GPU_Dialect, GPU_TransposeMode,
247+
"mat_transpose_mode">{
248+
let defaultValue = "TransposeMode::NON_TRANSPOSE";
249+
}
250+
251+
def GPU_SpGEMMWorkEstimationOrComputeKind : I32EnumAttr<"SpGEMMWorkEstimationOrComputeKind",
252+
"choose whether spgemm_work_estimation_or_compute does work estimation or compute",
253+
[
254+
I32EnumAttrCase<"WORK_ESTIMATION", 0>,
255+
I32EnumAttrCase<"COMPUTE", 1>,
256+
]> {
257+
let genSpecializedAttr = 0;
258+
let cppNamespace = GPU_Dialect.cppNamespace;
259+
}
260+
261+
def GPU_SpGEMMWorkEstimationOrComputeKindAttr : EnumAttr<GPU_Dialect,
262+
GPU_SpGEMMWorkEstimationOrComputeKind,
263+
"spgemm_work_estimation_or_compute_kind"> {}
264+
265+
102266
//===----------------------------------------------------------------------===//
103267
// GPU Types.
104268
//===----------------------------------------------------------------------===//

mlir/include/mlir/Dialect/GPU/IR/GPUOps.td

Lines changed: 0 additions & 164 deletions
Original file line numberDiff line numberDiff line change
@@ -38,18 +38,6 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
3838
class GPU_Op<string mnemonic, list<Trait> traits = []> :
3939
Op<GPU_Dialect, mnemonic, traits>;
4040

41-
def GPU_Dimension : I32EnumAttr<"Dimension",
42-
"a dimension, either 'x', 'y', or 'z'",
43-
[
44-
I32EnumAttrCase<"x", 0>,
45-
I32EnumAttrCase<"y", 1>,
46-
I32EnumAttrCase<"z", 2>
47-
]>{
48-
let genSpecializedAttr = 0;
49-
let cppNamespace = "::mlir::gpu";
50-
}
51-
def GPU_DimensionAttr : EnumAttr<GPU_Dialect, GPU_Dimension, "dim">;
52-
5341
class GPU_IndexOp<string mnemonic, list<Trait> traits = []> :
5442
GPU_Op<mnemonic, !listconcat(traits, [
5543
Pure,
@@ -1104,51 +1092,8 @@ def GPU_YieldOp : GPU_Op<"yield", [Pure, ReturnLike, Terminator]>,
11041092
let assemblyFormat = "attr-dict ($values^ `:` type($values))?";
11051093
}
11061094

1107-
// These mirror the reduction combining kinds from the vector dialect.
1108-
def GPU_AllReduceOpAdd : I32EnumAttrCase<"ADD", 0, "add">;
1109-
def GPU_AllReduceOpMul : I32EnumAttrCase<"MUL", 1, "mul">;
1110-
def GPU_AllReduceOpMinUI : I32EnumAttrCase<"MINUI", 2, "minui">;
1111-
def GPU_AllReduceOpMinSI : I32EnumAttrCase<"MINSI", 3, "minsi">;
1112-
// Follows the `arith.minnumf` semantics.
1113-
def GPU_AllReduceOpMinnumF : I32EnumAttrCase<"MINNUMF", 4, "minnumf">;
1114-
def GPU_AllReduceOpMaxUI : I32EnumAttrCase<"MAXUI", 5, "maxui">;
1115-
def GPU_AllReduceOpMaxSI : I32EnumAttrCase<"MAXSI", 6, "maxsi">;
1116-
// Follows the `arith.maxnumf` semantics.
1117-
def GPU_AllReduceOpMaxnumF : I32EnumAttrCase<"MAXNUMF", 7, "maxnumf">;
1118-
def GPU_AllReduceOpAnd : I32EnumAttrCase<"AND", 8, "and">;
1119-
def GPU_AllReduceOpOr : I32EnumAttrCase<"OR", 9, "or">;
1120-
def GPU_AllReduceOpXor : I32EnumAttrCase<"XOR", 10, "xor">;
1121-
// Follows the `arith.minimumf` semantics.
1122-
def GPU_AllReduceOpMinimumF : I32EnumAttrCase<"MINIMUMF", 11, "minimumf">;
1123-
// Follows the `arith.maximumf` semantics.
1124-
def GPU_AllReduceOpMaximumF : I32EnumAttrCase<"MAXIMUMF", 12, "maximumf">;
1125-
1126-
def GPU_AllReduceOperation : I32EnumAttr<"AllReduceOperation",
1127-
"built-in reduction operations supported by gpu.allreduce.",
1128-
[
1129-
GPU_AllReduceOpAdd,
1130-
GPU_AllReduceOpMul,
1131-
GPU_AllReduceOpMinUI,
1132-
GPU_AllReduceOpMinSI,
1133-
GPU_AllReduceOpMinnumF,
1134-
GPU_AllReduceOpMaxUI,
1135-
GPU_AllReduceOpMaxSI,
1136-
GPU_AllReduceOpMaxnumF,
1137-
GPU_AllReduceOpAnd,
1138-
GPU_AllReduceOpOr,
1139-
GPU_AllReduceOpXor,
1140-
GPU_AllReduceOpMinimumF,
1141-
GPU_AllReduceOpMaximumF
1142-
]>{
1143-
let genSpecializedAttr = 0;
1144-
let cppNamespace = "::mlir::gpu";
1145-
}
1146-
11471095
def AnyIntegerOrFloat : AnyTypeOf<[AnySignlessInteger, AnyFloat], "Integer or Float">;
11481096

1149-
def GPU_AllReduceOperationAttr : EnumAttr<GPU_Dialect, GPU_AllReduceOperation,
1150-
"all_reduce_op">;
1151-
11521097
def GPU_AllReduceOp : GPU_Op<"all_reduce",
11531098
[SameOperandsAndResultType, IsolatedFromAbove]> {
11541099
let summary = "Reduce values among workgroup.";
@@ -1276,22 +1221,6 @@ def GPU_SubgroupReduceOp : GPU_Op<"subgroup_reduce", [SameOperandsAndResultType]
12761221
let hasVerifier = 1;
12771222
}
12781223

1279-
def GPU_ShuffleOpXor : I32EnumAttrCase<"XOR", 0, "xor">;
1280-
def GPU_ShuffleOpDown : I32EnumAttrCase<"DOWN", 1, "down">;
1281-
def GPU_ShuffleOpUp : I32EnumAttrCase<"UP", 2, "up">;
1282-
def GPU_ShuffleOpIdx : I32EnumAttrCase<"IDX", 3, "idx">;
1283-
1284-
def GPU_ShuffleMode : I32EnumAttr<"ShuffleMode",
1285-
"Indexing modes supported by gpu.shuffle.",
1286-
[
1287-
GPU_ShuffleOpXor, GPU_ShuffleOpUp, GPU_ShuffleOpDown, GPU_ShuffleOpIdx,
1288-
]> {
1289-
let genSpecializedAttr = 0;
1290-
let cppNamespace = "::mlir::gpu";
1291-
}
1292-
def GPU_ShuffleModeAttr : EnumAttr<GPU_Dialect, GPU_ShuffleMode,
1293-
"shuffle_mode">;
1294-
12951224
def GPU_ShuffleOp : GPU_Op<
12961225
"shuffle", [Pure, AllTypesMatch<["value", "shuffleResult"]>]>,
12971226
Arguments<(ins AnyIntegerOrFloatOr1DVector:$value, I32:$offset, I32:$width,
@@ -1914,44 +1843,6 @@ def GPU_SubgroupMmaConstantMatrixOp : GPU_Op<"subgroup_mma_constant_matrix",
19141843
}];
19151844
}
19161845

1917-
def GPU_ElementwiseOpAddF : I32EnumAttrCase<"ADDF", 0, "addf">;
1918-
def GPU_ElementwiseOpMulF : I32EnumAttrCase<"MULF", 1, "mulf">;
1919-
def GPU_ElementwiseOpSUBF : I32EnumAttrCase<"SUBF", 2, "subf">;
1920-
def GPU_ElementwiseOpMaxF : I32EnumAttrCase<"MAXF", 3, "maxf">;
1921-
def GPU_ElementwiseOpMinF : I32EnumAttrCase<"MINF", 4, "minf">;
1922-
def GPU_ElementwiseOpDivF : I32EnumAttrCase<"DIVF", 5, "divf">;
1923-
def GPU_ElementwiseOpAddI : I32EnumAttrCase<"ADDI", 6, "addi">;
1924-
def GPU_ElementwiseOpMulI : I32EnumAttrCase<"MULI", 7, "muli">;
1925-
def GPU_ElementwiseOpSUBI : I32EnumAttrCase<"SUBI", 8, "subi">;
1926-
def GPU_ElementwiseOpDivS : I32EnumAttrCase<"DIVS", 9, "divs">;
1927-
def GPU_ElementwiseOpDivU : I32EnumAttrCase<"DIVU", 10, "divu">;
1928-
def GPU_ElementwiseOpNEGF : I32EnumAttrCase<"NEGATEF", 11, "negatef">;
1929-
def GPU_ElementwiseOpNEGS : I32EnumAttrCase<"NEGATES", 12, "negates">;
1930-
def GPU_ElementwiseOpEXTF : I32EnumAttrCase<"EXTF", 13, "extf">;
1931-
1932-
def MMAElementWise : I32EnumAttr<"MMAElementwiseOp",
1933-
"elementwise operation to apply to mma matrix", [
1934-
GPU_ElementwiseOpAddF,
1935-
GPU_ElementwiseOpMulF,
1936-
GPU_ElementwiseOpSUBF,
1937-
GPU_ElementwiseOpMaxF,
1938-
GPU_ElementwiseOpMinF,
1939-
GPU_ElementwiseOpDivF,
1940-
GPU_ElementwiseOpAddI,
1941-
GPU_ElementwiseOpMulI,
1942-
GPU_ElementwiseOpSUBI,
1943-
GPU_ElementwiseOpDivS,
1944-
GPU_ElementwiseOpDivU,
1945-
GPU_ElementwiseOpNEGF,
1946-
GPU_ElementwiseOpNEGS,
1947-
GPU_ElementwiseOpEXTF
1948-
]> {
1949-
let genSpecializedAttr = 0;
1950-
let cppNamespace = "::mlir::gpu";
1951-
}
1952-
def MMAElementWiseAttr : EnumAttr<GPU_Dialect, MMAElementWise,
1953-
"mma_element_wise">;
1954-
19551846
def GPU_SubgroupMmaElementwiseOp : GPU_Op<"subgroup_mma_elementwise",
19561847
[Pure,
19571848
AllTypesMatch<["args"]>]>{
@@ -2262,22 +2153,6 @@ def GPU_CreateBsrOp : GPU_Op<"create_bsr", [GPU_AsyncOpInterface]> {
22622153
}];
22632154
}
22642155

2265-
def GPU_Prune2To4SpMatFlag : I32EnumAttr<"Prune2To4SpMatFlag",
2266-
"pruning strategy for 2:4 sparse matrix",
2267-
[
2268-
I32EnumAttrCase<"NONE", 0>,
2269-
I32EnumAttrCase<"PRUNE_ONLY", 1>,
2270-
I32EnumAttrCase<"PRUNE_AND_CHECK", 2>,
2271-
]> {
2272-
let genSpecializedAttr = 0;
2273-
let cppNamespace = GPU_Dialect.cppNamespace;
2274-
}
2275-
2276-
def GPU_Prune2To4SpMatFlagAttr : EnumAttr<GPU_Dialect, GPU_Prune2To4SpMatFlag,
2277-
"prune_2to4_spmat_flag">{
2278-
let defaultValue = "Prune2To4SpMatFlag::PRUNE_AND_CHECK";
2279-
}
2280-
22812156

22822157
def GPU_Create2To4SpMatOp : GPU_Op<"create_2to4_spmat", [GPU_AsyncOpInterface]> {
22832158
let summary = "Create sparse matrix with 2:4 sparsity operation";
@@ -2340,31 +2215,6 @@ def GPU_DestroySpMatOp : GPU_Op<"destroy_sp_mat", [GPU_AsyncOpInterface]> {
23402215
}];
23412216
}
23422217

2343-
// To avoid coupling this dialect with cusparse.h specifics, we hardcoded magic
2344-
// literals in this enum. Note that this should be kept in sync with
2345-
// cusparseOperation_t in cusparse.h:
2346-
// typedef enum {
2347-
// CUSPARSE_OPERATION_NON_TRANSPOSE = 0,
2348-
// CUSPARSE_OPERATION_TRANSPOSE = 1,
2349-
// CUSPARSE_OPERATION_CONJUGATE_TRANSPOSE = 2
2350-
// } cusparseOperation_t;
2351-
// TODO: find a proper way to keep them in sync?
2352-
def GPU_TransposeMode : I32EnumAttr<"TransposeMode",
2353-
"transpose mode of sparse matrix supported by sparse tensor ops",
2354-
[
2355-
I32EnumAttrCase<"NON_TRANSPOSE", 0>,
2356-
I32EnumAttrCase<"TRANSPOSE", 1>,
2357-
I32EnumAttrCase<"CONJUGATE_TRANSPOSE", 2>,
2358-
]> {
2359-
let genSpecializedAttr = 0;
2360-
let cppNamespace = GPU_Dialect.cppNamespace;
2361-
}
2362-
2363-
def GPU_TransposeModeAttr : EnumAttr<GPU_Dialect, GPU_TransposeMode,
2364-
"mat_transpose_mode">{
2365-
let defaultValue = "TransposeMode::NON_TRANSPOSE";
2366-
}
2367-
23682218
def GPU_SpMVBufferSizeOp : GPU_Op<"spmv_buffer_size", [GPU_AsyncOpInterface]> {
23692219
let summary = "Precompute buffersize for SpMV operation";
23702220
let description = [{
@@ -2677,20 +2527,6 @@ def GPU_SDDMMOp : GPU_Op<"sddmm", [GPU_AsyncOpInterface]> {
26772527
}];
26782528
}
26792529

2680-
def GPU_SpGEMMWorkEstimationOrComputeKind : I32EnumAttr<"SpGEMMWorkEstimationOrComputeKind",
2681-
"choose whether spgemm_work_estimation_or_compute does work estimation or compute",
2682-
[
2683-
I32EnumAttrCase<"WORK_ESTIMATION", 0>,
2684-
I32EnumAttrCase<"COMPUTE", 1>,
2685-
]> {
2686-
let genSpecializedAttr = 0;
2687-
let cppNamespace = GPU_Dialect.cppNamespace;
2688-
}
2689-
2690-
def GPU_SpGEMMWorkEstimationOrComputeKindAttr : EnumAttr<GPU_Dialect,
2691-
GPU_SpGEMMWorkEstimationOrComputeKind,
2692-
"spgemm_work_estimation_or_compute_kind"> {}
2693-
26942530
def GPU_SpGEMMCreateDescrOp : GPU_Op<"spgemm_create_descr", [GPU_AsyncOpInterface]> {
26952531
let summary = "SpGEMM Create Descr operation";
26962532
let description = [{

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