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Use existing builtin.
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4 files changed

+18
-108
lines changed

4 files changed

+18
-108
lines changed

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -137,10 +137,6 @@ let TargetPrefix = "spv" in {
137137
: DefaultAttrsIntrinsic<[llvm_anyptr_ty], [llvm_any_ty, llvm_i32_ty],
138138
[IntrNoMem]>;
139139

140-
def int_spv_get_specialization_constant
141-
: DefaultAttrsIntrinsic<[llvm_any_ty], [llvm_i32_ty, LLVMMatchType<0>],
142-
[IntrNoMem, IntrWillReturn]>;
143-
144140
// Read a value from the image buffer. It does not translate directly to a
145141
// single OpImageRead because the result type is not necessarily a 4 element
146142
// vector.

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.td‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -674,6 +674,7 @@ defm : DemangledNativeBuiltin<"ndrange_3D", OpenCL_std, Enqueue, 1, 3, OpBuildND
674674

675675
// Spec constant builtin records:
676676
defm : DemangledNativeBuiltin<"__spirv_SpecConstant", OpenCL_std, SpecConstant, 2, 2, OpSpecConstant>;
677+
defm : DemangledNativeBuiltin<"__spirv_SpecConstant", GLSL_std_450, SpecConstant, 2, 2, OpSpecConstant>;
677678
defm : DemangledNativeBuiltin<"__spirv_SpecConstantComposite", OpenCL_std, SpecConstant, 1, 0, OpSpecConstantComposite>;
678679

679680
// Async Copy and Prefetch builtin records:

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 1 addition & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -296,22 +296,7 @@ class SPIRVInstructionSelector : public InstructionSelector {
296296
bool selectImageWriteIntrinsic(MachineInstr &I) const;
297297
bool selectResourceGetPointer(Register &ResVReg, const SPIRVType *ResType,
298298
MachineInstr &I) const;
299-
bool selectGetSpecializationConstant(Register &ResVReg,
300-
const SPIRVType *ResType,
301-
MachineInstr &I) const;
302-
303-
bool buildSpecConstant(llvm::MachineInstr &I, llvm::Register &ResVReg,
304-
llvm::SPIRVType *ResType,
305-
llvm::APInt &DefaultValue) const;
306-
307-
APInt getSpecConstantDefaultValue(llvm::MachineInstr &I) const;
308-
309-
bool buildBoolSpecConstant(Register &ResVReg, const SPIRVType *ResType,
310-
bool DefaultValue, MachineInstr &I) const;
311-
bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
312-
uint32_t DefaultValue, MachineInstr &I) const;
313-
bool buildIntegerSpecConstant(Register &ResVReg, const SPIRVType *ResType,
314-
uint64_t DefaultValue, MachineInstr &I) const;
299+
315300
// Utilities
316301
std::pair<Register, bool>
317302
buildI32Constant(uint32_t Val, MachineInstr &I,
@@ -3207,9 +3192,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
32073192
case Intrinsic::spv_resource_getpointer: {
32083193
return selectResourceGetPointer(ResVReg, ResType, I);
32093194
}
3210-
case Intrinsic::spv_get_specialization_constant: {
3211-
return selectGetSpecializationConstant(ResVReg, ResType, I);
3212-
}
32133195
case Intrinsic::spv_discard: {
32143196
return selectDiscard(ResVReg, ResType, I);
32153197
}
@@ -3327,84 +3309,6 @@ bool SPIRVInstructionSelector::selectResourceGetPointer(
33273309
.constrainAllUses(TII, TRI, RBI);
33283310
}
33293311

3330-
bool SPIRVInstructionSelector::buildBoolSpecConstant(Register &ResVReg,
3331-
const SPIRVType *ResType,
3332-
bool DefaultValue,
3333-
MachineInstr &I) const {
3334-
uint32_t Opc =
3335-
DefaultValue ? SPIRV::OpSpecConstantTrue : SPIRV::OpSpecConstantFalse;
3336-
return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc))
3337-
.addDef(ResVReg)
3338-
.addUse(GR.getSPIRVTypeID(ResType))
3339-
.constrainAllUses(TII, TRI, RBI);
3340-
}
3341-
3342-
bool SPIRVInstructionSelector::buildIntegerSpecConstant(
3343-
Register &ResVReg, const SPIRVType *ResType, uint32_t DefaultValue,
3344-
MachineInstr &I) const {
3345-
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
3346-
TII.get(SPIRV::OpSpecConstant))
3347-
.addDef(ResVReg)
3348-
.addUse(GR.getSPIRVTypeID(ResType))
3349-
.addImm(DefaultValue)
3350-
.constrainAllUses(TII, TRI, RBI);
3351-
}
3352-
3353-
bool SPIRVInstructionSelector::buildIntegerSpecConstant(
3354-
Register &ResVReg, const SPIRVType *ResType, uint64_t DefaultValue,
3355-
MachineInstr &I) const {
3356-
return BuildMI(*I.getParent(), I, I.getDebugLoc(),
3357-
TII.get(SPIRV::OpSpecConstant))
3358-
.addDef(ResVReg)
3359-
.addUse(GR.getSPIRVTypeID(ResType))
3360-
.addImm(DefaultValue & 0xFFFFFFFF)
3361-
.addImm(DefaultValue >> 32)
3362-
.constrainAllUses(TII, TRI, RBI);
3363-
}
3364-
3365-
bool SPIRVInstructionSelector::selectGetSpecializationConstant(
3366-
Register &ResVReg, const SPIRVType *ResType, MachineInstr &I) const {
3367-
uint32_t Id = foldImm(I.getOperand(2), MRI);
3368-
bool R = false;
3369-
APInt DefaultValue = getSpecConstantDefaultValue(I);
3370-
if (ResType->getOpcode() == SPIRV::OpTypeBool) {
3371-
R = buildBoolSpecConstant(ResVReg, ResType, DefaultValue.getBoolValue(), I);
3372-
} else {
3373-
R = buildSpecConstant(I, ResVReg, ResType, DefaultValue);
3374-
}
3375-
if (!R) {
3376-
return false;
3377-
}
3378-
buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::SpecId, {Id});
3379-
return R;
3380-
}
3381-
3382-
bool SPIRVInstructionSelector::buildSpecConstant(
3383-
llvm::MachineInstr &I, llvm::Register &ResVReg, llvm::SPIRVType *ResType,
3384-
llvm::APInt &DefaultValue) const {
3385-
auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(),
3386-
TII.get(SPIRV::OpSpecConstant))
3387-
.addDef(ResVReg)
3388-
.addUse(GR.getSPIRVTypeID(ResType));
3389-
addNumImm(DefaultValue, MIB);
3390-
return MIB.constrainAllUses(TII, TRI, RBI);
3391-
}
3392-
3393-
APInt SPIRVInstructionSelector::getSpecConstantDefaultValue(
3394-
llvm::MachineInstr &I) const {
3395-
APInt DefaultValue;
3396-
Register DefaultValueReg = I.getOperand(3).getReg();
3397-
auto *D = getDefInstrMaybeConstant(DefaultValueReg, MRI);
3398-
const auto &MO = D->getOperand(1);
3399-
if (MO.isCImm()) {
3400-
DefaultValue = MO.getCImm()->getValue();
3401-
} else {
3402-
assert(MO.isFPImm() && "");
3403-
DefaultValue = MO.getFPImm()->getValue().bitcastToAPInt();
3404-
}
3405-
return DefaultValue;
3406-
}
3407-
34083312
bool SPIRVInstructionSelector::extractSubvector(
34093313
Register &ResVReg, const SPIRVType *ResType, Register &ReadReg,
34103314
MachineInstr &InsertionPoint) const {

‎llvm/test/CodeGen/SPIRV/constant/spec-constant.ll‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -28,31 +28,40 @@
2828
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none)
2929
define void @main() local_unnamed_addr #0 {
3030
entry:
31-
%0 = tail call spir_func i1 @llvm.spv.get.specialization.constant.i1(i32 1, i1 true)
31+
%0 = tail call spir_func i1 @_Z20__spirv_SpecConstantib(i32 1, i1 true)
3232
%storedv.i.i = zext i1 %0 to i32
3333
store i32 %storedv.i.i, ptr addrspace(10) @_ZL10bool_const, align 4, !tbaa !3
3434
%1 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10bool_const)
35-
%2 = tail call spir_func i16 @llvm.spv.get.specialization.constant.i16(i32 2, i16 4)
35+
%2 = tail call spir_func i16 @_Z20__spirv_SpecConstantis(i32 2, i16 4)
3636
store i16 %2, ptr addrspace(10) @_ZL11short_const, align 2, !tbaa !7
3737
%3 = tail call ptr @llvm.invariant.start.p10(i64 2, ptr addrspace(10) @_ZL11short_const)
38-
%4 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 3, i32 5)
38+
%4 = tail call spir_func i32 @_Z20__spirv_SpecConstantii(i32 3, i32 5)
3939
store i32 %4, ptr addrspace(10) @_ZL9int_const, align 4, !tbaa !9
4040
%5 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL9int_const)
41-
%6 = tail call spir_func i64 @llvm.spv.get.specialization.constant.i64(i32 4, i64 8)
41+
%6 = tail call spir_func i64 @_Z20__spirv_SpecConstantix(i32 4, i64 8)
4242
store i64 %6, ptr addrspace(10) @_ZL10long_const, align 8, !tbaa !11
4343
%7 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL10long_const)
44-
%14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @llvm.spv.get.specialization.constant.f32(i32 8, float 5.000000e+01)
44+
%14 = tail call reassoc nnan ninf nsz arcp afn spir_func float @_Z20__spirv_SpecConstantif(i32 8, float 5.000000e+01)
4545
store float %14, ptr addrspace(10) @_ZL11float_const, align 4, !tbaa !13
4646
%15 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL11float_const)
47-
%16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @llvm.spv.get.specialization.constant.f64(i32 9, double 1.000000e+02)
47+
%16 = tail call reassoc nnan ninf nsz arcp afn spir_func double @_Z20__spirv_SpecConstantid(i32 9, double 1.000000e+02)
4848
store double %16, ptr addrspace(10) @_ZL12double_const, align 8, !tbaa !15
4949
%17 = tail call ptr @llvm.invariant.start.p10(i64 8, ptr addrspace(10) @_ZL12double_const)
50-
%18 = tail call spir_func i32 @llvm.spv.get.specialization.constant.i32(i32 10, i32 30)
50+
%18 = tail call spir_func i32 @_Z20__spirv_SpecConstantii(i32 10, i32 30)
5151
store i32 %18, ptr addrspace(10) @_ZL10enum_const, align 4, !tbaa !17
5252
%19 = tail call ptr @llvm.invariant.start.p10(i64 4, ptr addrspace(10) @_ZL10enum_const)
5353
ret void
5454
}
5555

56+
57+
declare i1 @_Z20__spirv_SpecConstantib(i32, i1)
58+
declare i8 @_Z20__spirv_SpecConstantia(i32, i8)
59+
declare i16 @_Z20__spirv_SpecConstantis(i32, i16)
60+
declare i32 @_Z20__spirv_SpecConstantii(i32, i32)
61+
declare i64 @_Z20__spirv_SpecConstantix(i32, i64)
62+
declare float @_Z20__spirv_SpecConstantif(i32, float)
63+
declare double @_Z20__spirv_SpecConstantid(i32, double)
64+
5665
attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: none, inaccessiblemem: none) "approx-func-fp-math"="true" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
5766
attributes #1 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
5867
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }

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