Skip to content

Commit abf6f85

Browse files
mshockwavemshockwave
committed
Pre-commit test
1 parent 2886576 commit abf6f85

File tree

1 file changed

+226
-0
lines changed

1 file changed

+226
-0
lines changed

‎llvm/test/CodeGen/RISCV/neg-abs.ll‎

Lines changed: 226 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -258,3 +258,229 @@ define i64 @neg_abs64_multiuse(i64 %x, ptr %y) {
258258
%neg = sub nsw i64 0, %abs
259259
ret i64 %neg
260260
}
261+
262+
define i32 @expanded_neg_abs32(i32 %x) {
263+
; RV32I-LABEL: expanded_neg_abs32:
264+
; RV32I: # %bb.0:
265+
; RV32I-NEXT: neg a1, a0
266+
; RV32I-NEXT: blt a0, a1, .LBB6_2
267+
; RV32I-NEXT: # %bb.1:
268+
; RV32I-NEXT: mv a1, a0
269+
; RV32I-NEXT: .LBB6_2:
270+
; RV32I-NEXT: neg a0, a1
271+
; RV32I-NEXT: ret
272+
;
273+
; RV32ZBB-LABEL: expanded_neg_abs32:
274+
; RV32ZBB: # %bb.0:
275+
; RV32ZBB-NEXT: neg a1, a0
276+
; RV32ZBB-NEXT: max a0, a1, a0
277+
; RV32ZBB-NEXT: neg a0, a0
278+
; RV32ZBB-NEXT: ret
279+
;
280+
; RV64I-LABEL: expanded_neg_abs32:
281+
; RV64I: # %bb.0:
282+
; RV64I-NEXT: sext.w a1, a0
283+
; RV64I-NEXT: negw a0, a0
284+
; RV64I-NEXT: blt a1, a0, .LBB6_2
285+
; RV64I-NEXT: # %bb.1:
286+
; RV64I-NEXT: mv a0, a1
287+
; RV64I-NEXT: .LBB6_2:
288+
; RV64I-NEXT: negw a0, a0
289+
; RV64I-NEXT: ret
290+
;
291+
; RV64ZBB-LABEL: expanded_neg_abs32:
292+
; RV64ZBB: # %bb.0:
293+
; RV64ZBB-NEXT: sext.w a1, a0
294+
; RV64ZBB-NEXT: negw a0, a0
295+
; RV64ZBB-NEXT: max a0, a0, a1
296+
; RV64ZBB-NEXT: negw a0, a0
297+
; RV64ZBB-NEXT: ret
298+
%n = sub i32 0, %x
299+
%t = call i32 @llvm.smax.i32(i32 %n, i32 %x)
300+
%r = sub i32 0, %t
301+
ret i32 %r
302+
}
303+
304+
define i32 @expanded_neg_abs32_unsigned(i32 %x) {
305+
; RV32I-LABEL: expanded_neg_abs32_unsigned:
306+
; RV32I: # %bb.0:
307+
; RV32I-NEXT: neg a1, a0
308+
; RV32I-NEXT: bltu a0, a1, .LBB7_2
309+
; RV32I-NEXT: # %bb.1:
310+
; RV32I-NEXT: mv a1, a0
311+
; RV32I-NEXT: .LBB7_2:
312+
; RV32I-NEXT: neg a0, a1
313+
; RV32I-NEXT: ret
314+
;
315+
; RV32ZBB-LABEL: expanded_neg_abs32_unsigned:
316+
; RV32ZBB: # %bb.0:
317+
; RV32ZBB-NEXT: neg a1, a0
318+
; RV32ZBB-NEXT: maxu a0, a1, a0
319+
; RV32ZBB-NEXT: neg a0, a0
320+
; RV32ZBB-NEXT: ret
321+
;
322+
; RV64I-LABEL: expanded_neg_abs32_unsigned:
323+
; RV64I: # %bb.0:
324+
; RV64I-NEXT: sext.w a1, a0
325+
; RV64I-NEXT: negw a0, a0
326+
; RV64I-NEXT: bltu a1, a0, .LBB7_2
327+
; RV64I-NEXT: # %bb.1:
328+
; RV64I-NEXT: mv a0, a1
329+
; RV64I-NEXT: .LBB7_2:
330+
; RV64I-NEXT: negw a0, a0
331+
; RV64I-NEXT: ret
332+
;
333+
; RV64ZBB-LABEL: expanded_neg_abs32_unsigned:
334+
; RV64ZBB: # %bb.0:
335+
; RV64ZBB-NEXT: sext.w a1, a0
336+
; RV64ZBB-NEXT: negw a0, a0
337+
; RV64ZBB-NEXT: maxu a0, a0, a1
338+
; RV64ZBB-NEXT: negw a0, a0
339+
; RV64ZBB-NEXT: ret
340+
%n = sub i32 0, %x
341+
%t = call i32 @llvm.umax.i32(i32 %n, i32 %x)
342+
%r = sub i32 0, %t
343+
ret i32 %r
344+
}
345+
346+
define i64 @expanded_neg_abs64(i64 %x) {
347+
; RV32I-LABEL: expanded_neg_abs64:
348+
; RV32I: # %bb.0:
349+
; RV32I-NEXT: snez a2, a0
350+
; RV32I-NEXT: neg a3, a1
351+
; RV32I-NEXT: sub a2, a3, a2
352+
; RV32I-NEXT: neg a3, a0
353+
; RV32I-NEXT: beq a2, a1, .LBB8_2
354+
; RV32I-NEXT: # %bb.1:
355+
; RV32I-NEXT: slt a4, a1, a2
356+
; RV32I-NEXT: beqz a4, .LBB8_3
357+
; RV32I-NEXT: j .LBB8_4
358+
; RV32I-NEXT: .LBB8_2:
359+
; RV32I-NEXT: sltu a4, a0, a3
360+
; RV32I-NEXT: bnez a4, .LBB8_4
361+
; RV32I-NEXT: .LBB8_3:
362+
; RV32I-NEXT: mv a2, a1
363+
; RV32I-NEXT: mv a3, a0
364+
; RV32I-NEXT: .LBB8_4:
365+
; RV32I-NEXT: snez a0, a3
366+
; RV32I-NEXT: add a0, a2, a0
367+
; RV32I-NEXT: neg a1, a0
368+
; RV32I-NEXT: neg a0, a3
369+
; RV32I-NEXT: ret
370+
;
371+
; RV32ZBB-LABEL: expanded_neg_abs64:
372+
; RV32ZBB: # %bb.0:
373+
; RV32ZBB-NEXT: snez a2, a0
374+
; RV32ZBB-NEXT: neg a3, a1
375+
; RV32ZBB-NEXT: sub a2, a3, a2
376+
; RV32ZBB-NEXT: neg a3, a0
377+
; RV32ZBB-NEXT: beq a2, a1, .LBB8_2
378+
; RV32ZBB-NEXT: # %bb.1:
379+
; RV32ZBB-NEXT: slt a4, a1, a2
380+
; RV32ZBB-NEXT: beqz a4, .LBB8_3
381+
; RV32ZBB-NEXT: j .LBB8_4
382+
; RV32ZBB-NEXT: .LBB8_2:
383+
; RV32ZBB-NEXT: sltu a4, a0, a3
384+
; RV32ZBB-NEXT: bnez a4, .LBB8_4
385+
; RV32ZBB-NEXT: .LBB8_3:
386+
; RV32ZBB-NEXT: mv a2, a1
387+
; RV32ZBB-NEXT: mv a3, a0
388+
; RV32ZBB-NEXT: .LBB8_4:
389+
; RV32ZBB-NEXT: snez a0, a3
390+
; RV32ZBB-NEXT: add a0, a2, a0
391+
; RV32ZBB-NEXT: neg a1, a0
392+
; RV32ZBB-NEXT: neg a0, a3
393+
; RV32ZBB-NEXT: ret
394+
;
395+
; RV64I-LABEL: expanded_neg_abs64:
396+
; RV64I: # %bb.0:
397+
; RV64I-NEXT: neg a1, a0
398+
; RV64I-NEXT: blt a0, a1, .LBB8_2
399+
; RV64I-NEXT: # %bb.1:
400+
; RV64I-NEXT: mv a1, a0
401+
; RV64I-NEXT: .LBB8_2:
402+
; RV64I-NEXT: neg a0, a1
403+
; RV64I-NEXT: ret
404+
;
405+
; RV64ZBB-LABEL: expanded_neg_abs64:
406+
; RV64ZBB: # %bb.0:
407+
; RV64ZBB-NEXT: neg a1, a0
408+
; RV64ZBB-NEXT: max a0, a1, a0
409+
; RV64ZBB-NEXT: neg a0, a0
410+
; RV64ZBB-NEXT: ret
411+
%n = sub i64 0, %x
412+
%t = call i64 @llvm.smax.i64(i64 %n, i64 %x)
413+
%r = sub i64 0, %t
414+
ret i64 %r
415+
}
416+
417+
define i64 @expanded_neg_abs64_unsigned(i64 %x) {
418+
; RV32I-LABEL: expanded_neg_abs64_unsigned:
419+
; RV32I: # %bb.0:
420+
; RV32I-NEXT: snez a2, a0
421+
; RV32I-NEXT: neg a3, a1
422+
; RV32I-NEXT: sub a2, a3, a2
423+
; RV32I-NEXT: neg a3, a0
424+
; RV32I-NEXT: beq a2, a1, .LBB9_2
425+
; RV32I-NEXT: # %bb.1:
426+
; RV32I-NEXT: sltu a4, a1, a2
427+
; RV32I-NEXT: beqz a4, .LBB9_3
428+
; RV32I-NEXT: j .LBB9_4
429+
; RV32I-NEXT: .LBB9_2:
430+
; RV32I-NEXT: sltu a4, a0, a3
431+
; RV32I-NEXT: bnez a4, .LBB9_4
432+
; RV32I-NEXT: .LBB9_3:
433+
; RV32I-NEXT: mv a2, a1
434+
; RV32I-NEXT: mv a3, a0
435+
; RV32I-NEXT: .LBB9_4:
436+
; RV32I-NEXT: snez a0, a3
437+
; RV32I-NEXT: add a0, a2, a0
438+
; RV32I-NEXT: neg a1, a0
439+
; RV32I-NEXT: neg a0, a3
440+
; RV32I-NEXT: ret
441+
;
442+
; RV32ZBB-LABEL: expanded_neg_abs64_unsigned:
443+
; RV32ZBB: # %bb.0:
444+
; RV32ZBB-NEXT: snez a2, a0
445+
; RV32ZBB-NEXT: neg a3, a1
446+
; RV32ZBB-NEXT: sub a2, a3, a2
447+
; RV32ZBB-NEXT: neg a3, a0
448+
; RV32ZBB-NEXT: beq a2, a1, .LBB9_2
449+
; RV32ZBB-NEXT: # %bb.1:
450+
; RV32ZBB-NEXT: sltu a4, a1, a2
451+
; RV32ZBB-NEXT: beqz a4, .LBB9_3
452+
; RV32ZBB-NEXT: j .LBB9_4
453+
; RV32ZBB-NEXT: .LBB9_2:
454+
; RV32ZBB-NEXT: sltu a4, a0, a3
455+
; RV32ZBB-NEXT: bnez a4, .LBB9_4
456+
; RV32ZBB-NEXT: .LBB9_3:
457+
; RV32ZBB-NEXT: mv a2, a1
458+
; RV32ZBB-NEXT: mv a3, a0
459+
; RV32ZBB-NEXT: .LBB9_4:
460+
; RV32ZBB-NEXT: snez a0, a3
461+
; RV32ZBB-NEXT: add a0, a2, a0
462+
; RV32ZBB-NEXT: neg a1, a0
463+
; RV32ZBB-NEXT: neg a0, a3
464+
; RV32ZBB-NEXT: ret
465+
;
466+
; RV64I-LABEL: expanded_neg_abs64_unsigned:
467+
; RV64I: # %bb.0:
468+
; RV64I-NEXT: neg a1, a0
469+
; RV64I-NEXT: bltu a0, a1, .LBB9_2
470+
; RV64I-NEXT: # %bb.1:
471+
; RV64I-NEXT: mv a1, a0
472+
; RV64I-NEXT: .LBB9_2:
473+
; RV64I-NEXT: neg a0, a1
474+
; RV64I-NEXT: ret
475+
;
476+
; RV64ZBB-LABEL: expanded_neg_abs64_unsigned:
477+
; RV64ZBB: # %bb.0:
478+
; RV64ZBB-NEXT: neg a1, a0
479+
; RV64ZBB-NEXT: maxu a0, a1, a0
480+
; RV64ZBB-NEXT: neg a0, a0
481+
; RV64ZBB-NEXT: ret
482+
%n = sub i64 0, %x
483+
%t = call i64 @llvm.umax.i64(i64 %n, i64 %x)
484+
%r = sub i64 0, %t
485+
ret i64 %r
486+
}

0 commit comments

Comments
 (0)