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‎llvm/test/CodeGen/RISCV/shifts.ll‎

Lines changed: 299 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -484,3 +484,302 @@ define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
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%res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)
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ret i128 %res
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}
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define i64 @lshr64_shamt32(i64 %a, i32 signext %b) nounwind {
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; RV32I-LABEL: lshr64_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a4, a2, -32
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; RV32I-NEXT: srl a3, a1, a2
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; RV32I-NEXT: bltz a4, .LBB11_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: j .LBB11_3
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; RV32I-NEXT: .LBB11_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: not a2, a2
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; RV32I-NEXT: slli a1, a1, 1
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: .LBB11_3:
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; RV32I-NEXT: srai a1, a4, 31
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: lshr64_shamt32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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%zext = zext nneg i32 %b to i64
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%1 = lshr i64 %a, %zext
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ret i64 %1
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}
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define i64 @ashr64_shamt32(i64 %a, i32 signext %b) nounwind {
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; RV32I-LABEL: ashr64_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a3, a1
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; RV32I-NEXT: addi a4, a2, -32
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; RV32I-NEXT: sra a1, a1, a2
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; RV32I-NEXT: bltz a4, .LBB12_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srai a3, a3, 31
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB12_2:
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: not a2, a2
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; RV32I-NEXT: slli a3, a3, 1
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; RV32I-NEXT: sll a2, a3, a2
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ashr64_shamt32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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%zext = zext nneg i32 %b to i64
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%1 = ashr i64 %a, %zext
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ret i64 %1
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}
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define i64 @shl64_shamt32(i64 %a, i32 signext %b) nounwind {
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; RV32I-LABEL: shl64_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a4, a2, -32
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; RV32I-NEXT: sll a3, a0, a2
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; RV32I-NEXT: bltz a4, .LBB13_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: j .LBB13_3
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; RV32I-NEXT: .LBB13_2:
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: not a2, a2
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a1, a1, a0
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; RV32I-NEXT: .LBB13_3:
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; RV32I-NEXT: srai a0, a4, 31
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; RV32I-NEXT: and a0, a0, a3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: shl64_shamt32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sll a0, a0, a1
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; RV64I-NEXT: ret
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%zext = zext nneg i32 %b to i64
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%1 = shl i64 %a, %zext
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ret i64 %1
573+
}
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define i128 @lshr128_shamt32(i128 %a, i32 signext %b) nounwind {
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; RV32I-LABEL: lshr128_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: lw a4, 4(a1)
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; RV32I-NEXT: lw a5, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: sw zero, 16(sp)
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; RV32I-NEXT: sw zero, 20(sp)
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; RV32I-NEXT: sw zero, 24(sp)
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; RV32I-NEXT: sw zero, 28(sp)
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; RV32I-NEXT: srli a6, a2, 3
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; RV32I-NEXT: mv a7, sp
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; RV32I-NEXT: andi t0, a2, 31
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; RV32I-NEXT: andi a6, a6, 12
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; RV32I-NEXT: xori t0, t0, 31
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; RV32I-NEXT: add a6, a7, a6
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; RV32I-NEXT: sw a3, 0(sp)
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; RV32I-NEXT: sw a4, 4(sp)
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; RV32I-NEXT: sw a5, 8(sp)
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; RV32I-NEXT: sw a1, 12(sp)
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; RV32I-NEXT: lw a1, 0(a6)
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; RV32I-NEXT: lw a3, 4(a6)
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; RV32I-NEXT: lw a4, 8(a6)
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; RV32I-NEXT: lw a5, 12(a6)
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: slli a6, a3, 1
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; RV32I-NEXT: srl a3, a3, a2
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; RV32I-NEXT: slli a7, a4, 1
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; RV32I-NEXT: srl a4, a4, a2
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; RV32I-NEXT: srl a2, a5, a2
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; RV32I-NEXT: slli a5, a5, 1
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; RV32I-NEXT: sll a6, a6, t0
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; RV32I-NEXT: sll a7, a7, t0
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; RV32I-NEXT: sll a5, a5, t0
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; RV32I-NEXT: or a1, a1, a6
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; RV32I-NEXT: or a3, a3, a7
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; RV32I-NEXT: or a4, a4, a5
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: sw a3, 4(a0)
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; RV32I-NEXT: sw a4, 8(a0)
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; RV32I-NEXT: sw a2, 12(a0)
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; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: lshr128_shamt32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a4, a2, 32
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; RV64I-NEXT: srli a4, a4, 32
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; RV64I-NEXT: addi a3, a4, -64
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; RV64I-NEXT: bltz a3, .LBB14_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: srl a0, a1, a4
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; RV64I-NEXT: j .LBB14_3
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; RV64I-NEXT: .LBB14_2:
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; RV64I-NEXT: srl a0, a0, a2
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; RV64I-NEXT: slli a5, a1, 1
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; RV64I-NEXT: not a4, a4
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; RV64I-NEXT: sll a4, a5, a4
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; RV64I-NEXT: or a0, a0, a4
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; RV64I-NEXT: .LBB14_3:
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; RV64I-NEXT: srl a1, a1, a2
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; RV64I-NEXT: srai a3, a3, 63
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; RV64I-NEXT: and a1, a3, a1
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; RV64I-NEXT: ret
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%zext = zext nneg i32 %b to i128
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%1 = lshr i128 %a, %zext
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ret i128 %1
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}
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define i128 @ashr128_shamt32(i128 %a, i32 signext %b) nounwind {
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; RV32I-LABEL: ashr128_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: lw a4, 4(a1)
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; RV32I-NEXT: lw a5, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: srli a6, a2, 3
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; RV32I-NEXT: mv a7, sp
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; RV32I-NEXT: andi t0, a2, 31
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; RV32I-NEXT: andi a6, a6, 12
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; RV32I-NEXT: xori t0, t0, 31
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; RV32I-NEXT: add a6, a7, a6
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; RV32I-NEXT: sw a3, 0(sp)
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; RV32I-NEXT: sw a4, 4(sp)
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; RV32I-NEXT: sw a5, 8(sp)
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; RV32I-NEXT: sw a1, 12(sp)
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: sw a1, 16(sp)
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; RV32I-NEXT: sw a1, 20(sp)
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; RV32I-NEXT: sw a1, 24(sp)
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; RV32I-NEXT: sw a1, 28(sp)
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; RV32I-NEXT: lw a1, 0(a6)
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; RV32I-NEXT: lw a3, 4(a6)
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; RV32I-NEXT: lw a4, 8(a6)
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; RV32I-NEXT: lw a5, 12(a6)
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: slli a6, a3, 1
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; RV32I-NEXT: srl a3, a3, a2
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; RV32I-NEXT: slli a7, a4, 1
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; RV32I-NEXT: srl a4, a4, a2
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; RV32I-NEXT: sra a2, a5, a2
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; RV32I-NEXT: slli a5, a5, 1
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; RV32I-NEXT: sll a6, a6, t0
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; RV32I-NEXT: sll a7, a7, t0
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; RV32I-NEXT: sll a5, a5, t0
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; RV32I-NEXT: or a1, a1, a6
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; RV32I-NEXT: or a3, a3, a7
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; RV32I-NEXT: or a4, a4, a5
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: sw a3, 4(a0)
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; RV32I-NEXT: sw a4, 8(a0)
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; RV32I-NEXT: sw a2, 12(a0)
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; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ashr128_shamt32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a3, a2, 32
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; RV64I-NEXT: srli a3, a3, 32
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; RV64I-NEXT: addi a4, a3, -64
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; RV64I-NEXT: bltz a4, .LBB15_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: sra a0, a1, a3
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; RV64I-NEXT: srai a1, a1, 63
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB15_2:
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; RV64I-NEXT: srl a0, a0, a2
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; RV64I-NEXT: slli a4, a1, 1
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; RV64I-NEXT: not a3, a3
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; RV64I-NEXT: sll a3, a4, a3
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; RV64I-NEXT: or a0, a0, a3
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; RV64I-NEXT: sra a1, a1, a2
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; RV64I-NEXT: ret
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%zext = zext nneg i32 %b to i128
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%1 = ashr i128 %a, %zext
713+
ret i128 %1
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}
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define i128 @shl128_shamt32(i128 %a, i32 signext %b) nounwind {
717+
; RV32I-LABEL: shl128_shamt32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -32
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; RV32I-NEXT: lw a3, 0(a1)
721+
; RV32I-NEXT: lw a4, 4(a1)
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; RV32I-NEXT: lw a5, 8(a1)
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; RV32I-NEXT: lw a1, 12(a1)
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; RV32I-NEXT: sw zero, 0(sp)
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; RV32I-NEXT: sw zero, 4(sp)
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; RV32I-NEXT: sw zero, 8(sp)
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; RV32I-NEXT: sw zero, 12(sp)
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; RV32I-NEXT: srli a6, a2, 3
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; RV32I-NEXT: addi a7, sp, 16
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; RV32I-NEXT: andi t0, a2, 31
731+
; RV32I-NEXT: andi a6, a6, 12
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; RV32I-NEXT: sub a6, a7, a6
733+
; RV32I-NEXT: sw a3, 16(sp)
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; RV32I-NEXT: sw a4, 20(sp)
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; RV32I-NEXT: sw a5, 24(sp)
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; RV32I-NEXT: sw a1, 28(sp)
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; RV32I-NEXT: lw a1, 0(a6)
738+
; RV32I-NEXT: lw a3, 4(a6)
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; RV32I-NEXT: lw a4, 8(a6)
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; RV32I-NEXT: lw a5, 12(a6)
741+
; RV32I-NEXT: xori a6, t0, 31
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; RV32I-NEXT: sll a7, a3, a2
743+
; RV32I-NEXT: srli t0, a1, 1
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; RV32I-NEXT: sll a5, a5, a2
745+
; RV32I-NEXT: sll a1, a1, a2
746+
; RV32I-NEXT: sll a2, a4, a2
747+
; RV32I-NEXT: srli a3, a3, 1
748+
; RV32I-NEXT: srli a4, a4, 1
749+
; RV32I-NEXT: srl t0, t0, a6
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; RV32I-NEXT: srl a3, a3, a6
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; RV32I-NEXT: srl a4, a4, a6
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; RV32I-NEXT: or a6, a7, t0
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; RV32I-NEXT: or a2, a2, a3
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; RV32I-NEXT: or a4, a5, a4
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: sw a6, 4(a0)
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; RV32I-NEXT: sw a2, 8(a0)
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; RV32I-NEXT: sw a4, 12(a0)
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; RV32I-NEXT: addi sp, sp, 32
760+
; RV32I-NEXT: ret
761+
;
762+
; RV64I-LABEL: shl128_shamt32:
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; RV64I: # %bb.0:
764+
; RV64I-NEXT: slli a4, a2, 32
765+
; RV64I-NEXT: srli a4, a4, 32
766+
; RV64I-NEXT: addi a3, a4, -64
767+
; RV64I-NEXT: bltz a3, .LBB16_2
768+
; RV64I-NEXT: # %bb.1:
769+
; RV64I-NEXT: sll a1, a0, a4
770+
; RV64I-NEXT: j .LBB16_3
771+
; RV64I-NEXT: .LBB16_2:
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; RV64I-NEXT: sll a1, a1, a2
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; RV64I-NEXT: srli a5, a0, 1
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; RV64I-NEXT: not a4, a4
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; RV64I-NEXT: srl a4, a5, a4
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; RV64I-NEXT: or a1, a1, a4
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; RV64I-NEXT: .LBB16_3:
778+
; RV64I-NEXT: sll a0, a0, a2
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; RV64I-NEXT: srai a3, a3, 63
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; RV64I-NEXT: and a0, a3, a0
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; RV64I-NEXT: ret
782+
%zext = zext nneg i32 %b to i128
783+
%1 = shl i128 %a, %zext
784+
ret i128 %1
785+
}

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