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[AMDGPU] Precommit test for memory intrinics CGP handling
Change-Id: Id229f849b1d8552bbe59d6e18114042ef1614fad
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‎llvm/test/CodeGen/AMDGPU/sink-addr-memory-intrinsics.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s
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define amdgpu_kernel void @memoryIntrinstic(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr) {
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; CHECK-LABEL: memoryIntrinstic:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_and_b32 s1, s1, 1
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; CHECK-NEXT: s_add_i32 s3, s0, 0x2000
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; CHECK-NEXT: s_cmp_eq_u32 s1, 0
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; CHECK-NEXT: s_cbranch_scc0 .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %else
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; CHECK-NEXT: v_mov_b32_e32 v0, s3
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: s_mov_b32 s0, 0x7060302
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; CHECK-NEXT: s_mov_b32 s1, 0x5040100
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s1
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; CHECK-NEXT: s_cbranch_execz .LBB0_3
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; CHECK-NEXT: s_branch .LBB0_4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: ; implicit-def: $vgpr1
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; CHECK-NEXT: .LBB0_3: ; %then
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; CHECK-NEXT: v_mov_b32_e32 v0, s3
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: s_mov_b32 s0, 0x5040100
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; CHECK-NEXT: s_mov_b32 s1, 0x7060302
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s1
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; CHECK-NEXT: .LBB0_4: ; %end
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: ds_write_b64 v2, v[0:1]
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; CHECK-NEXT: s_endpgm
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%gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 2048
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br i1 %cond, label %then, label %else
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then:
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%load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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%shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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br label %end
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else:
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%load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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%shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
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br label %end
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end:
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%res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]
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store <4 x half> %res, ptr addrspace(3) %outptr
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ret void
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}
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define amdgpu_kernel void @badIntrinsicUse(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr, <4 x i32> %rsrc) {
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; CHECK-LABEL: badIntrinsicUse:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_and_b32 s1, s1, 1
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; CHECK-NEXT: s_add_i32 s3, s0, 0x2000
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; CHECK-NEXT: s_cmp_eq_u32 s1, 0
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; CHECK-NEXT: s_cbranch_scc0 .LBB1_2
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; CHECK-NEXT: ; %bb.1: ; %else
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; CHECK-NEXT: v_mov_b32_e32 v0, s3
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; CHECK-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: s_mov_b32 s0, 0x7060302
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: s_mov_b32 s0, 0x5040100
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s0
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; CHECK-NEXT: s_cbranch_execz .LBB1_3
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; CHECK-NEXT: s_branch .LBB1_4
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: ; implicit-def: $vgpr1
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; CHECK-NEXT: .LBB1_3: ; %then
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; CHECK-NEXT: v_mov_b32_e32 v0, s3
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: s_mov_b32 s0, 0x5040100
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; CHECK-NEXT: s_mov_b32 s1, 0x7060302
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s1
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; CHECK-NEXT: .LBB1_4: ; %end
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: ds_write_b64 v2, v[0:1]
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; CHECK-NEXT: s_endpgm
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%gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 2048
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br i1 %cond, label %then, label %else
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then:
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%load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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%shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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br label %end
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else:
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%load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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call void @llvm.amdgcn.raw.buffer.store(ptr addrspace(3) %gep0, <4 x i32> %rsrc, i32 0, i32 0, i32 0)
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%shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
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br label %end
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end:
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%res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]
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store <4 x half> %res, ptr addrspace(3) %outptr
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ret void
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}
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define amdgpu_kernel void @badIntrinsicUse2(ptr addrspace(3) %inptr, i1 %cond, ptr addrspace(3) %outptr, ptr addrspace(3) %outptr1) {
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; CHECK-LABEL: badIntrinsicUse2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_and_b32 s1, s1, 1
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; CHECK-NEXT: s_add_i32 s4, s0, 0x2000
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; CHECK-NEXT: s_cmp_eq_u32 s1, 0
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; CHECK-NEXT: s_cbranch_scc0 .LBB2_2
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; CHECK-NEXT: ; %bb.1: ; %else
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: v_mov_b32_e32 v0, s3
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; CHECK-NEXT: v_mov_b32_e32 v1, s4
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; CHECK-NEXT: s_mov_b32 s0, 0x7060302
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; CHECK-NEXT: ds_write_b32 v0, v1
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; CHECK-NEXT: s_waitcnt lgkmcnt(1)
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: s_mov_b32 s0, 0x5040100
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s0
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; CHECK-NEXT: s_cbranch_execz .LBB2_3
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; CHECK-NEXT: s_branch .LBB2_4
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: ; implicit-def: $vgpr1
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; CHECK-NEXT: .LBB2_3: ; %then
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; CHECK-NEXT: v_mov_b32_e32 v0, s4
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; CHECK-NEXT: ds_read_b64_tr_b16 v[2:3], v0
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; CHECK-NEXT: s_mov_b32 s0, 0x5040100
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; CHECK-NEXT: s_mov_b32 s1, 0x7060302
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_perm_b32 v0, v3, v2, s0
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; CHECK-NEXT: v_perm_b32 v1, v3, v2, s1
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; CHECK-NEXT: .LBB2_4: ; %end
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: ds_write_b64 v2, v[0:1]
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; CHECK-NEXT: s_endpgm
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%gep0 = getelementptr ptr addrspace(3), ptr addrspace(3) %inptr, i32 2048
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br i1 %cond, label %then, label %else
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then:
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%load0 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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%shuf0 = shufflevector <4 x half> %load0, <4 x half> %load0, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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br label %end
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else:
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%load1 = tail call <4 x half> @llvm.amdgcn.ds.read.tr16.b64.v4f16(ptr addrspace(3) %gep0)
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%gep1 = call ptr addrspace(3) @llvm.amdgcn.readfirstlane(ptr addrspace(3) %gep0)
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store ptr addrspace(3) %gep1, ptr addrspace(3) %outptr1
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%shuf1 = shufflevector <4 x half> %load1, <4 x half> %load1, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
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br label %end
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end:
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%res = phi <4 x half> [ %shuf0, %then ], [ %shuf1, %else ]
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store <4 x half> %res, ptr addrspace(3) %outptr
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ret void
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}

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