Skip to content

Commit accb451

Browse files
LU-JOHNLU-JOHN
committed
Invert uses to delete s_cmp_eq*
Signed-off-by: John Lu <[email protected]>
1 parent 6d18313 commit accb451

File tree

6 files changed

+117
-36
lines changed

6 files changed

+117
-36
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 63 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10621,12 +10621,64 @@ bool SIInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1062110621
return false;
1062210622
}
1062310623

10624+
bool SIInstrInfo::invertSCCUse(MachineInstr *SCCDef) const {
10625+
MachineBasicBlock *MBB = SCCDef->getParent();
10626+
const SIRegisterInfo *TRI = ST.getRegisterInfo();
10627+
SmallVector<MachineInstr *, 2> InvertInstr;
10628+
bool SCCIsDead = false;
10629+
10630+
// Scan instructions for SCC uses that need to be inverted until SCC is dead.
10631+
for (MachineInstr &MI :
10632+
make_range(std::next(MachineBasicBlock::iterator(SCCDef)), MBB->end())) {
10633+
if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, TRI, false) != -1) {
10634+
if (MI.getOpcode() == AMDGPU::S_CSELECT_B32 ||
10635+
MI.getOpcode() == AMDGPU::S_CSELECT_B64 ||
10636+
MI.getOpcode() == AMDGPU::S_CBRANCH_SCC0 ||
10637+
MI.getOpcode() == AMDGPU::S_CBRANCH_SCC1)
10638+
InvertInstr.push_back(&MI);
10639+
else
10640+
return false;
10641+
}
10642+
if (MI.modifiesRegister(AMDGPU::SCC, TRI)) {
10643+
SCCIsDead = true;
10644+
break;
10645+
}
10646+
}
10647+
10648+
const MachineRegisterInfo &MRI =
10649+
SCCDef->getParent()->getParent()->getRegInfo();
10650+
// If SCC is still live, verify that it is not live past the end of this
10651+
// block.
10652+
if (!SCCIsDead && MRI.tracksLiveness())
10653+
SCCIsDead = MBB->computeRegisterLiveness(TRI, AMDGPU::SCC, MBB->end(), 0) ==
10654+
MachineBasicBlock::LQR_Dead;
10655+
10656+
// Invert uses
10657+
if (SCCIsDead) {
10658+
for (auto &MI : InvertInstr) {
10659+
if (MI->getOpcode() == AMDGPU::S_CSELECT_B32 ||
10660+
MI->getOpcode() == AMDGPU::S_CSELECT_B64)
10661+
swapOperands(*MI);
10662+
else if (MI->getOpcode() == AMDGPU::S_CBRANCH_SCC0 ||
10663+
MI->getOpcode() == AMDGPU::S_CBRANCH_SCC1)
10664+
MI->setDesc(get(MI->getOpcode() == AMDGPU::S_CBRANCH_SCC0
10665+
? AMDGPU::S_CBRANCH_SCC1
10666+
: AMDGPU::S_CBRANCH_SCC0));
10667+
else
10668+
llvm_unreachable("SCC used but no inversion handling");
10669+
}
10670+
return true;
10671+
}
10672+
return false;
10673+
}
10674+
1062410675
// SCC is already valid after SCCValid.
1062510676
// SCCRedefine will redefine SCC to the same value already available after
1062610677
// SCCValid. If there are no intervening SCC conflicts delete SCCRedefine and
1062710678
// update kill/dead flags if necessary.
10628-
static bool optimizeSCC(MachineInstr *SCCValid, MachineInstr *SCCRedefine,
10629-
const SIRegisterInfo &RI) {
10679+
bool SIInstrInfo::optimizeSCC(MachineInstr *SCCValid, MachineInstr *SCCRedefine,
10680+
const SIRegisterInfo &RI,
10681+
bool NeedInversion) const {
1063010682
MachineInstr *KillsSCC = nullptr;
1063110683
if (SCCValid->getParent() != SCCRedefine->getParent())
1063210684
return false;
@@ -10637,6 +10689,8 @@ static bool optimizeSCC(MachineInstr *SCCValid, MachineInstr *SCCRedefine,
1063710689
if (MI.killsRegister(AMDGPU::SCC, &RI))
1063810690
KillsSCC = &MI;
1063910691
}
10692+
if (NeedInversion && !invertSCCUse(SCCRedefine))
10693+
return false;
1064010694
if (MachineOperand *SccDef =
1064110695
SCCValid->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr))
1064210696
SccDef->setIsDead(false);
@@ -10670,7 +10724,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1067010724
return false;
1067110725

1067210726
const auto optimizeCmpSelect = [&CmpInstr, SrcReg, CmpValue, MRI,
10673-
this]() -> bool {
10727+
this](bool NeedInversion) -> bool {
1067410728
if (CmpValue != 0)
1067510729
return false;
1067610730

@@ -10691,7 +10745,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1069110745
if (!setsSCCifResultIsNonZero(*Def) && !foldableSelect(*Def))
1069210746
return false;
1069310747

10694-
if (!optimizeSCC(Def, &CmpInstr, RI))
10748+
if (!optimizeSCC(Def, &CmpInstr, RI, NeedInversion))
1069510749
return false;
1069610750

1069710751
// If s_or_b32 result, sY, is unused (i.e. it is effectively a 64-bit
@@ -10716,7 +10770,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1071610770
Def1->getOperand(1).getReg() == Def2->getOperand(1).getReg()) {
1071710771
MachineInstr *Select = MRI->getVRegDef(Def1->getOperand(1).getReg());
1071810772
if (Select && foldableSelect(*Select))
10719-
optimizeSCC(Select, Def, RI);
10773+
optimizeSCC(Select, Def, RI, false);
1072010774
}
1072110775
}
1072210776
}
@@ -10797,7 +10851,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1079710851
if (IsReversedCC && !MRI->hasOneNonDBGUse(DefReg))
1079810852
return false;
1079910853

10800-
if (!optimizeSCC(Def, &CmpInstr, RI))
10854+
if (!optimizeSCC(Def, &CmpInstr, RI, false))
1080110855
return false;
1080210856

1080310857
if (!MRI->use_nodbg_empty(DefReg)) {
@@ -10828,7 +10882,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1082810882
case AMDGPU::S_CMP_EQ_I32:
1082910883
case AMDGPU::S_CMPK_EQ_U32:
1083010884
case AMDGPU::S_CMPK_EQ_I32:
10831-
return optimizeCmpAnd(1, 32, true, false);
10885+
return optimizeCmpAnd(1, 32, true, false) || optimizeCmpSelect(true);
1083210886
case AMDGPU::S_CMP_GE_U32:
1083310887
case AMDGPU::S_CMPK_GE_U32:
1083410888
return optimizeCmpAnd(1, 32, false, false);
@@ -10841,15 +10895,15 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1084110895
case AMDGPU::S_CMP_LG_I32:
1084210896
case AMDGPU::S_CMPK_LG_U32:
1084310897
case AMDGPU::S_CMPK_LG_I32:
10844-
return optimizeCmpAnd(0, 32, true, false) || optimizeCmpSelect();
10898+
return optimizeCmpAnd(0, 32, true, false) || optimizeCmpSelect(false);
1084510899
case AMDGPU::S_CMP_GT_U32:
1084610900
case AMDGPU::S_CMPK_GT_U32:
1084710901
return optimizeCmpAnd(0, 32, false, false);
1084810902
case AMDGPU::S_CMP_GT_I32:
1084910903
case AMDGPU::S_CMPK_GT_I32:
1085010904
return optimizeCmpAnd(0, 32, false, true);
1085110905
case AMDGPU::S_CMP_LG_U64:
10852-
return optimizeCmpAnd(0, 64, true, false) || optimizeCmpSelect();
10906+
return optimizeCmpAnd(0, 64, true, false) || optimizeCmpSelect(false);
1085310907
}
1085410908

1085510909
return false;

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
125125
unsigned SubIdx, const TargetRegisterClass *SubRC) const;
126126

127127
private:
128+
bool optimizeSCC(MachineInstr *SCCValid, MachineInstr *SCCRedefine,
129+
const SIRegisterInfo &RI, bool NeedInversion) const;
130+
131+
bool invertSCCUse(MachineInstr *SCCDef) const;
132+
128133
void swapOperands(MachineInstr &Inst) const;
129134

130135
std::pair<bool, MachineBasicBlock *>

‎llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -702,11 +702,10 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
702702
; GFX90A-NEXT: successors: %bb.59(0x40000000), %bb.53(0x40000000)
703703
; GFX90A-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr3, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9:0x000000000000000F, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr24_sgpr25, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $sgpr50_sgpr51, $sgpr56_sgpr57:0x000000000000000F, $sgpr62_sgpr63, $sgpr66_sgpr67, $sgpr20_sgpr21_sgpr22_sgpr23:0x000000000000003F, $sgpr24_sgpr25_sgpr26_sgpr27:0x00000000000000F0, $vgpr0_vgpr1:0x000000000000000F, $vgpr2_vgpr3:0x0000000000000003, $vgpr4_vgpr5:0x000000000000000F, $vgpr6_vgpr7:0x000000000000000F, $vgpr40_vgpr41:0x000000000000000F, $vgpr42_vgpr43:0x000000000000000F, $vgpr44_vgpr45:0x000000000000000F, $vgpr46_vgpr47:0x000000000000000F, $vgpr56_vgpr57:0x000000000000000F, $vgpr58_vgpr59:0x0000000000000003, $vgpr60_vgpr61:0x000000000000000F, $vgpr62_vgpr63:0x000000000000000F, $sgpr0_sgpr1_sgpr2_sgpr3
704704
; GFX90A-NEXT: {{ $}}
705-
; GFX90A-NEXT: renamable $sgpr17 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def dead $scc
706-
; GFX90A-NEXT: S_CMP_EQ_U32 killed renamable $sgpr17, 0, implicit-def $scc
705+
; GFX90A-NEXT: dead renamable $sgpr17 = S_BFE_U32 renamable $sgpr20, 65560, implicit-def $scc
707706
; GFX90A-NEXT: renamable $vgpr8 = V_ADD_CO_U32_e32 4096, $vgpr0, implicit-def $vcc, implicit $exec
708707
; GFX90A-NEXT: renamable $vgpr9, dead renamable $sgpr18_sgpr19 = V_ADDC_U32_e64 0, 0, killed $vcc, 0, implicit $exec
709-
; GFX90A-NEXT: S_CBRANCH_SCC1 %bb.59, implicit killed $scc
708+
; GFX90A-NEXT: S_CBRANCH_SCC0 %bb.59, implicit killed $scc
710709
; GFX90A-NEXT: {{ $}}
711710
; GFX90A-NEXT: bb.53:
712711
; GFX90A-NEXT: successors: %bb.61(0x80000000)

‎llvm/test/CodeGen/AMDGPU/fshl.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -695,8 +695,7 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
695695
; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
696696
; SI-NEXT: s_lshl_b32 s6, s4, 7
697697
; SI-NEXT: s_or_b32 s6, s5, s6
698-
; SI-NEXT: s_cmp_eq_u32 s6, 0
699-
; SI-NEXT: s_cselect_b32 s4, s4, s5
698+
; SI-NEXT: s_cselect_b32 s4, s5, s4
700699
; SI-NEXT: s_mov_b32 s3, 0xf000
701700
; SI-NEXT: s_mov_b32 s2, -1
702701
; SI-NEXT: v_mov_b32_e32 v0, s4
@@ -709,8 +708,7 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
709708
; VI-NEXT: s_waitcnt lgkmcnt(0)
710709
; VI-NEXT: s_lshl_b32 s4, s2, 7
711710
; VI-NEXT: s_or_b32 s4, s3, s4
712-
; VI-NEXT: s_cmp_eq_u32 s4, 0
713-
; VI-NEXT: s_cselect_b32 s2, s2, s3
711+
; VI-NEXT: s_cselect_b32 s2, s3, s2
714712
; VI-NEXT: v_mov_b32_e32 v0, s0
715713
; VI-NEXT: v_mov_b32_e32 v1, s1
716714
; VI-NEXT: v_mov_b32_e32 v2, s2
@@ -724,8 +722,7 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
724722
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
725723
; GFX9-NEXT: s_lshl_b32 s4, s2, 7
726724
; GFX9-NEXT: s_or_b32 s4, s3, s4
727-
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
728-
; GFX9-NEXT: s_cselect_b32 s2, s2, s3
725+
; GFX9-NEXT: s_cselect_b32 s2, s3, s2
729726
; GFX9-NEXT: v_mov_b32_e32 v1, s2
730727
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
731728
; GFX9-NEXT: s_endpgm
@@ -751,8 +748,7 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
751748
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
752749
; GFX10-NEXT: s_lshl_b32 s4, s2, 7
753750
; GFX10-NEXT: s_or_b32 s4, s3, s4
754-
; GFX10-NEXT: s_cmp_eq_u32 s4, 0
755-
; GFX10-NEXT: s_cselect_b32 s2, s2, s3
751+
; GFX10-NEXT: s_cselect_b32 s2, s3, s2
756752
; GFX10-NEXT: v_mov_b32_e32 v1, s2
757753
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
758754
; GFX10-NEXT: s_endpgm
@@ -762,11 +758,9 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
762758
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
763759
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
764760
; GFX11-NEXT: s_lshl_b32 s4, s2, 7
765-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
761+
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
766762
; GFX11-NEXT: s_or_b32 s4, s3, s4
767-
; GFX11-NEXT: s_cmp_eq_u32 s4, 0
768-
; GFX11-NEXT: s_cselect_b32 s2, s2, s3
769-
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
763+
; GFX11-NEXT: s_cselect_b32 s2, s3, s2
770764
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
771765
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
772766
; GFX11-NEXT: s_endpgm

‎llvm/test/CodeGen/AMDGPU/s_cmp_0.ll‎

Lines changed: 38 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
3+
; Test deletion of redundant s_cmp* sX, 0 instructions.
34

45
declare i32 @llvm.ctpop.i32(i32)
56
declare i64 @llvm.ctpop.i64(i64)
@@ -20,6 +21,38 @@ define amdgpu_ps i32 @shl32(i32 inreg %val0, i32 inreg %val1) {
2021
ret i32 %zext
2122
}
2223

24+
; s_lshl_b32 sets SCC if result is non-zero.
25+
; Deletion of equal to zero comparison will require inversion of use.
26+
define amdgpu_ps i32 @shl32_eq(i32 inreg %val0, i32 inreg %val1) {
27+
; CHECK-LABEL: shl32_eq:
28+
; CHECK: ; %bb.0:
29+
; CHECK-NEXT: s_lshl_b32 s0, s0, s1
30+
; CHECK-NEXT: s_cselect_b64 s[0:1], 0, -1
31+
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
32+
; CHECK-NEXT: v_readfirstlane_b32 s0, v0
33+
; CHECK-NEXT: ; return to shader part epilog
34+
%result = shl i32 %val0, %val1
35+
%cmp = icmp eq i32 %result, 0
36+
%zext = zext i1 %cmp to i32
37+
ret i32 %zext
38+
}
39+
40+
; 64-bit selection will generate two 32-bit selects. Inversion of multiple
41+
; uses is required.
42+
define amdgpu_ps i64 @shl32_eq_multi_use(i32 inreg %val0, i64 inreg %val1) {
43+
; CHECK-LABEL: shl32_eq_multi_use:
44+
; CHECK: ; %bb.0:
45+
; CHECK-NEXT: s_lshl_b32 s0, s0, 1
46+
; CHECK-NEXT: s_cselect_b32 s2, 0, s2
47+
; CHECK-NEXT: s_cselect_b32 s0, 0, s1
48+
; CHECK-NEXT: s_mov_b32 s1, s2
49+
; CHECK-NEXT: ; return to shader part epilog
50+
%result = shl i32 %val0, 1
51+
%cmp = icmp eq i32 %result, 0
52+
%val64 = select i1 %cmp, i64 %val1, i64 0
53+
ret i64 %val64
54+
}
55+
2356
define amdgpu_ps i32 @shl64(i64 inreg %val0, i64 inreg %val1) {
2457
; CHECK-LABEL: shl64:
2558
; CHECK: ; %bb.0:
@@ -623,14 +656,14 @@ define amdgpu_ps i32 @si_pc_add_rel_offset_must_not_optimize() {
623656
; CHECK-NEXT: s_add_u32 s0, s0, __unnamed_1@rel32@lo+4
624657
; CHECK-NEXT: s_addc_u32 s1, s1, __unnamed_1@rel32@hi+12
625658
; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
626-
; CHECK-NEXT: s_cbranch_scc0 .LBB36_2
659+
; CHECK-NEXT: s_cbranch_scc0 .LBB38_2
627660
; CHECK-NEXT: ; %bb.1: ; %endif
628661
; CHECK-NEXT: s_mov_b32 s0, 1
629-
; CHECK-NEXT: s_branch .LBB36_3
630-
; CHECK-NEXT: .LBB36_2: ; %if
662+
; CHECK-NEXT: s_branch .LBB38_3
663+
; CHECK-NEXT: .LBB38_2: ; %if
631664
; CHECK-NEXT: s_mov_b32 s0, 0
632-
; CHECK-NEXT: s_branch .LBB36_3
633-
; CHECK-NEXT: .LBB36_3:
665+
; CHECK-NEXT: s_branch .LBB38_3
666+
; CHECK-NEXT: .LBB38_3:
634667
%cmp = icmp ne ptr addrspace(4) @1, null
635668
br i1 %cmp, label %endif, label %if
636669

‎llvm/test/CodeGen/AMDGPU/workitem-intrinsic-opts.ll‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -180,8 +180,7 @@ define i1 @workgroup_zero() {
180180
; DAGISEL-GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
181181
; DAGISEL-GFX8-NEXT: s_or_b32 s4, s12, s13
182182
; DAGISEL-GFX8-NEXT: s_or_b32 s4, s4, s14
183-
; DAGISEL-GFX8-NEXT: s_cmp_eq_u32 s4, 0
184-
; DAGISEL-GFX8-NEXT: s_cselect_b64 s[4:5], -1, 0
183+
; DAGISEL-GFX8-NEXT: s_cselect_b64 s[4:5], 0, -1
185184
; DAGISEL-GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
186185
; DAGISEL-GFX8-NEXT: s_setpc_b64 s[30:31]
187186
;
@@ -190,8 +189,7 @@ define i1 @workgroup_zero() {
190189
; DAGISEL-GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
191190
; DAGISEL-GFX942-NEXT: s_or_b32 s0, s12, s13
192191
; DAGISEL-GFX942-NEXT: s_or_b32 s0, s0, s14
193-
; DAGISEL-GFX942-NEXT: s_cmp_eq_u32 s0, 0
194-
; DAGISEL-GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0
192+
; DAGISEL-GFX942-NEXT: s_cselect_b64 s[0:1], 0, -1
195193
; DAGISEL-GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
196194
; DAGISEL-GFX942-NEXT: s_setpc_b64 s[30:31]
197195
;
@@ -208,9 +206,7 @@ define i1 @workgroup_zero() {
208206
; DAGISEL-GFX12-NEXT: s_or_b32 s0, ttmp9, s0
209207
; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
210208
; DAGISEL-GFX12-NEXT: s_or_b32 s0, s0, s1
211-
; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
212-
; DAGISEL-GFX12-NEXT: s_cmp_eq_u32 s0, 0
213-
; DAGISEL-GFX12-NEXT: s_cselect_b32 s0, -1, 0
209+
; DAGISEL-GFX12-NEXT: s_cselect_b32 s0, 0, -1
214210
; DAGISEL-GFX12-NEXT: s_wait_alu 0xfffe
215211
; DAGISEL-GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
216212
; DAGISEL-GFX12-NEXT: s_setpc_b64 s[30:31]

0 commit comments

Comments
 (0)