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phoebewangtru
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[X86][FP16] Promote FP16->[U]INT to FP16->FP32->[U]INT
This is to avoid f16->i64 being lowered to `__fixhfdi/__fixunshfdi` on 32-bits since neither libgcc nor compiler-rt provide them. https://godbolt.org/z/cjWEsea5v It also helps to improve the performance by promoting the vector type. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D131828 (cherry picked from commit 8b69549)
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llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32705,8 +32705,29 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3270532705
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
3270632706
EVT VT = N->getValueType(0);
3270732707
SDValue Src = N->getOperand(IsStrict ? 1 : 0);
32708+
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3270832709
EVT SrcVT = Src.getValueType();
3270932710

32711+
SDValue Res;
32712+
if (isSoftFP16(SrcVT)) {
32713+
EVT NVT = VT.isVector() ? VT.changeVectorElementType(MVT::f32) : MVT::f32;
32714+
if (IsStrict) {
32715+
Res =
32716+
DAG.getNode(N->getOpcode(), dl, {VT, MVT::Other},
32717+
{Chain, DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
32718+
{NVT, MVT::Other}, {Chain, Src})});
32719+
Chain = Res.getValue(1);
32720+
} else {
32721+
Res = DAG.getNode(N->getOpcode(), dl, VT,
32722+
DAG.getNode(ISD::FP_EXTEND, dl, NVT, Src));
32723+
}
32724+
Results.push_back(Res);
32725+
if (IsStrict)
32726+
Results.push_back(Chain);
32727+
32728+
return;
32729+
}
32730+
3271032731
if (VT.isVector() && Subtarget.hasFP16() &&
3271132732
SrcVT.getVectorElementType() == MVT::f16) {
3271232733
EVT EleVT = VT.getVectorElementType();
@@ -32720,7 +32741,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3272032741
Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8f16, Ops);
3272132742
}
3272232743

32723-
SDValue Res, Chain;
3272432744
if (IsStrict) {
3272532745
unsigned Opc =
3272632746
IsSigned ? X86ISD::STRICT_CVTTP2SI : X86ISD::STRICT_CVTTP2UI;
@@ -32912,7 +32932,6 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
3291232932
return;
3291332933
}
3291432934

32915-
SDValue Chain;
3291632935
if (SDValue V = FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, Chain)) {
3291732936
Results.push_back(V);
3291832937
if (IsStrict)

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