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akshayrdeodharakshayrdeodhar
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address review comments
1 parent 9ff3279 commit acd31be

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4 files changed

+35
-42
lines changed

4 files changed

+35
-42
lines changed

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp‎

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ bool NVPTXDAGToDAGISel::tryEXTRACT_VECTOR_ELEMENT(SDNode *N) {
487487
return true;
488488
}
489489

490-
static std::optional<unsigned> convertAS(unsigned AS) {
490+
static std::optional<NVPTX::AddressSpace> convertAS(unsigned AS) {
491491
switch (AS) {
492492
case llvm::ADDRESS_SPACE_LOCAL:
493493
return NVPTX::AddressSpace::Local;
@@ -508,17 +508,12 @@ static std::optional<unsigned> convertAS(unsigned AS) {
508508
}
509509
}
510510

511-
static unsigned int getCodeAddrSpace(const MemSDNode *N) {
511+
NVPTX::AddressSpace NVPTXDAGToDAGISel::getAddrSpace(const MemSDNode *N) {
512512
return convertAS(N->getMemOperand()->getAddrSpace())
513513
.value_or(NVPTX::AddressSpace::Generic);
514514
}
515515

516-
unsigned int NVPTXDAGToDAGISel::getAddrSpace(const MemSDNode *N) const {
517-
return convertAS(N->getMemOperand()->getAddrSpace())
518-
.value_or(NVPTX::AddressSpace::Generic);
519-
}
520-
521-
unsigned int NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
516+
NVPTX::Ordering NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
522517
// No "sem" orderings for SM/PTX versions which do not support memory ordering
523518
if (!Subtarget->hasMemoryOrdering())
524519
return NVPTX::Ordering::NotAtomic;
@@ -540,7 +535,7 @@ unsigned int NVPTXDAGToDAGISel::getMemOrder(const MemSDNode *N) const {
540535
}
541536
}
542537

543-
unsigned int NVPTXDAGToDAGISel::getAtomicScope(const MemSDNode *N) const {
538+
NVPTX::Scope NVPTXDAGToDAGISel::getAtomicScope(const MemSDNode *N) const {
544539
// No "scope" modifier for SM/PTX versions which do not support scoped atomics
545540
if (!Subtarget->hasAtomScope())
546541
return NVPTX::Scope::Thread;
@@ -559,7 +554,7 @@ struct OperationOrderings {
559554
static OperationOrderings
560555
getOperationOrderings(MemSDNode *N, const NVPTXSubtarget *Subtarget) {
561556
AtomicOrdering Ordering = N->getSuccessOrdering();
562-
auto CodeAddrSpace = getCodeAddrSpace(N);
557+
auto CodeAddrSpace = NVPTXDAGToDAGISel::getAddrSpace(N);
563558

564559
bool HasMemoryOrdering = Subtarget->hasMemoryOrdering();
565560
bool HasRelaxedMMIO = Subtarget->hasRelaxedMMIO();
@@ -1051,7 +1046,7 @@ bool NVPTXDAGToDAGISel::tryLoad(SDNode *N) {
10511046
const MVT LoadedVT = LoadedEVT.getSimpleVT();
10521047

10531048
// Address Space Setting
1054-
const unsigned CodeAddrSpace = getCodeAddrSpace(LD);
1049+
const unsigned CodeAddrSpace = getAddrSpace(LD);
10551050
if (canLowerToLDG(*LD, *Subtarget, CodeAddrSpace))
10561051
return tryLDG(LD);
10571052

@@ -1123,7 +1118,7 @@ bool NVPTXDAGToDAGISel::tryLoadVector(SDNode *N) {
11231118
const MVT MemVT = MemEVT.getSimpleVT();
11241119

11251120
// Address Space Setting
1126-
const unsigned CodeAddrSpace = getCodeAddrSpace(LD);
1121+
const unsigned CodeAddrSpace = getAddrSpace(LD);
11271122
if (canLowerToLDG(*LD, *Subtarget, CodeAddrSpace))
11281123
return tryLDG(LD);
11291124

@@ -1339,7 +1334,7 @@ bool NVPTXDAGToDAGISel::tryStore(SDNode *N) {
13391334
return false;
13401335

13411336
// Address Space Setting
1342-
const unsigned CodeAddrSpace = getCodeAddrSpace(ST);
1337+
const unsigned CodeAddrSpace = getAddrSpace(ST);
13431338

13441339
SDLoc DL(ST);
13451340
SDValue Chain = ST->getChain();
@@ -1389,7 +1384,7 @@ bool NVPTXDAGToDAGISel::tryStoreVector(SDNode *N) {
13891384
assert(StoreVT.isSimple() && "Store value is not simple");
13901385

13911386
// Address Space Setting
1392-
const unsigned CodeAddrSpace = getCodeAddrSpace(ST);
1387+
const unsigned CodeAddrSpace = getAddrSpace(ST);
13931388
if (CodeAddrSpace == NVPTX::AddressSpace::Const) {
13941389
report_fatal_error("Cannot store to pointer that points to constant "
13951390
"memory space");

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -102,9 +102,8 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
102102
inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
103103
return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
104104
}
105-
unsigned int getAddrSpace(const MemSDNode *N) const;
106-
unsigned int getMemOrder(const MemSDNode *N) const;
107-
unsigned int getAtomicScope(const MemSDNode *N) const;
105+
NVPTX::Ordering getMemOrder(const MemSDNode *N) const;
106+
NVPTX::Scope getAtomicScope(const MemSDNode *N) const;
108107

109108
bool SelectADDR(SDValue Addr, SDValue &Base, SDValue &Offset);
110109
SDValue getPTXCmpMode(const CondCodeSDNode &CondCode);
@@ -119,6 +118,9 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
119118
std::pair<NVPTX::Ordering, NVPTX::Scope>
120119
insertMemoryInstructionFence(SDLoc DL, SDValue &Chain, MemSDNode *N);
121120
NVPTX::Scope getOperationScope(MemSDNode *N, NVPTX::Ordering O) const;
121+
122+
public:
123+
static NVPTX::AddressSpace getAddrSpace(const MemSDNode *N);
122124
};
123125

124126
class NVPTXDAGToDAGISelLegacy : public SelectionDAGISelLegacy {

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6275,7 +6275,7 @@ Instruction *NVPTXTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
62756275
SyncScope::ID SSID = cast<AtomicCmpXchgInst>(Inst)->getSyncScopeID();
62766276
if (isReleaseOrStronger(Ord))
62776277
return Builder.CreateFence(Ord == AtomicOrdering::SequentiallyConsistent
6278-
? AtomicOrdering::SequentiallyConsistent
6278+
? Ord
62796279
: AtomicOrdering::Release,
62806280
SSID);
62816281

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td‎

Lines changed: 20 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1881,29 +1881,27 @@ multiclass F_ATOMIC_2<RegTyInfo t, string sem_str, string as_str, string op_str,
18811881
}
18821882
}
18831883

1884-
multiclass F_ATOMIC_3<RegTyInfo t, string op_str> {
1885-
defvar asm_str = "atom${sem:sem}${scope:scope}${addsp:addsp}" # op_str # "\t$dst, [$addr], $b, $c;";
1884+
multiclass F_ATOMIC_3<RegTyInfo t, string op_str, SDPatternOperator op, SDNode atomic> {
1885+
defvar asm_str = "atom${sem:sem}${scope:scope}${addsp:addsp}" # op_str;
18861886

18871887
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
1888-
def _rr : NVPTXInst<(outs t.RC:$dst),
1889-
(ins ADDR:$addr, t.RC:$b, t.RC:$c, AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
1888+
def _rr : BasicFlagsNVPTXInst<(outs t.RC:$dst),
1889+
(ins ADDR:$addr, t.RC:$b, t.RC:$c), (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
18901890
asm_str, []>;
18911891

1892-
def _ir : NVPTXInst<(outs t.RC:$dst),
1893-
(ins ADDR:$addr, t.Imm:$b, t.RC:$c, AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
1892+
def _ir : BasicFlagsNVPTXInst<(outs t.RC:$dst),
1893+
(ins ADDR:$addr, t.Imm:$b, t.RC:$c), (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
18941894
asm_str, []>;
18951895

1896-
def _ri : NVPTXInst<(outs t.RC:$dst),
1897-
(ins ADDR:$addr, t.RC:$b, t.Imm:$c, AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
1896+
def _ri : BasicFlagsNVPTXInst<(outs t.RC:$dst),
1897+
(ins ADDR:$addr, t.RC:$b, t.Imm:$c), (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
18981898
asm_str, []>;
18991899

1900-
def _ii : NVPTXInst<(outs t.RC:$dst),
1901-
(ins ADDR:$addr, t.Imm:$b, t.Imm:$c, AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
1900+
def _ii : BasicFlagsNVPTXInst<(outs t.RC:$dst),
1901+
(ins ADDR:$addr, t.Imm:$b, t.Imm:$c), (ins AtomicCode:$sem, AtomicCode:$scope, AtomicCode:$addsp),
19021902
asm_str, []>;
19031903
}
1904-
}
19051904

1906-
multiclass F_ATOMIC_3_PATTERN<RegTyInfo t, string InstructionName, SDPatternOperator op, SDNode atomic> {
19071905
defvar GetSem = SDNodeXForm<atomic, [{
19081906
return getI32Imm(getMemOrder(cast<MemSDNode>(N)), SDLoc(N));
19091907
}]>;
@@ -1917,16 +1915,16 @@ multiclass F_ATOMIC_3_PATTERN<RegTyInfo t, string InstructionName, SDPatternOper
19171915
}]>;
19181916

19191917
def : Pat<(op:$this addr:$addr, t.Ty:$b, t.Ty:$c),
1920-
(!cast<Instruction>(InstructionName#_rr) ADDR:$addr, t.Ty:$b, t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>;
1918+
(!cast<Instruction>(NAME # _rr) ADDR:$addr, t.Ty:$b, t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>;
19211919

19221920
def : Pat<(op:$this addr:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c),
1923-
(!cast<Instruction>(InstructionName#_ir) ADDR:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>;
1921+
(!cast<Instruction>(NAME # _ir) ADDR:$addr, (t.Ty t.ImmNode:$b), t.Ty:$c, (GetSem $this), (GetScope $this), (GetAddSp $this))>;
19241922

19251923
def : Pat<(op:$this addr:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c)),
1926-
(!cast<Instruction>(InstructionName#_#ri) ADDR:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>;
1924+
(!cast<Instruction>(NAME # _#ri) ADDR:$addr, t.Ty:$b, (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>;
19271925

19281926
def : Pat<(op:$this addr:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c)),
1929-
(!cast<Instruction>(InstructionName#_#ii) ADDR:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>;
1927+
(!cast<Instruction>(NAME # _#ii) ADDR:$addr, (t.Ty t.ImmNode:$b), (t.Ty t.ImmNode:$c), (GetSem $this), (GetScope $this), (GetAddSp $this))>;
19301928
}
19311929

19321930
multiclass F_ATOMIC_2_AS<RegTyInfo t, SDPatternOperator frag, string op_str, list<Predicate> preds = []> {
@@ -1984,9 +1982,7 @@ defm INT_PTX_ATOM_XOR_64 : F_ATOMIC_2_AS<I64RT, atomic_load_xor_i64, "xor.b64",
19841982
foreach t = [I16RT, I32RT, I64RT] in {
19851983
defvar atomic_cmp_swap_pat = !cast<PatFrag>("atomic_cmp_swap_i"#t.Size);
19861984
defm INT_PTX_ATOM_CAS_#t.Size
1987-
: F_ATOMIC_3<t, ".cas.b"#t.Size>;
1988-
1989-
defm INT_PTX_ATOM_CAS_PAT_#t.Size : F_ATOMIC_3_PATTERN<t, "INT_PTX_ATOM_CAS_"#t.Size, atomic_cmp_swap_pat, atomic_cmp_swap>;
1985+
: F_ATOMIC_3<t, ".cas.b"#t.Size, atomic_cmp_swap_pat, atomic_cmp_swap>;
19901986
}
19911987

19921988
// Support for scoped atomic operations. Matches
@@ -2027,10 +2023,10 @@ multiclass ATOM2S_impl<string OpStr, string IntTypeStr, string TypeStr,
20272023
}
20282024
}
20292025

2030-
multiclass F_ATOMIC_3_INTRINSIC_PATTERN<RegTyInfo t, string OpStr, string InstructionName, string IntTypeStr> {
2026+
multiclass F_ATOMIC_3_INTRINSIC_PATTERN<RegTyInfo t, string OpStr, string InstructionName> {
20312027
foreach scope = ["cta", "sys"] in {
20322028
foreach space = ["gen"] in {
2033-
defvar intrinsic = !cast<SDPatternOperator>("int_nvvm_atomic_" # OpStr # "_" # space # "_" # IntTypeStr # "_" # scope);
2029+
defvar intrinsic = !cast<SDPatternOperator>("int_nvvm_atomic_" # OpStr # "_" # space # "_i_" # scope);
20342030
def : Pat<(t.Ty (intrinsic addr:$addr, t.Ty:$b, t.Ty:$c)),
20352031
(!cast<Instruction>(InstructionName # "_rr") ADDR:$addr, t.Ty:$b, t.Ty:$c, Ordering_not_atomic, !cast<PatLeaf>("Scope_" # scope), !cast<PatLeaf>("AddrSpace_" # space))>;
20362032

@@ -2084,9 +2080,9 @@ multiclass ATOM2_incdec_impl<string OpStr> {
20842080

20852081
// atom.cas
20862082
multiclass ATOM3_cas_impl<string OpStr> {
2087-
defm _b16 : F_ATOMIC_3_INTRINSIC_PATTERN<I16RT, OpStr, "INT_PTX_ATOM_CAS_16", "i">;
2088-
defm _b32 : F_ATOMIC_3_INTRINSIC_PATTERN<I32RT, OpStr, "INT_PTX_ATOM_CAS_32", "i">;
2089-
defm _b64 : F_ATOMIC_3_INTRINSIC_PATTERN<I64RT, OpStr, "INT_PTX_ATOM_CAS_64", "i">;
2083+
defm _b16 : F_ATOMIC_3_INTRINSIC_PATTERN<I16RT, OpStr, "INT_PTX_ATOM_CAS_16">;
2084+
defm _b32 : F_ATOMIC_3_INTRINSIC_PATTERN<I32RT, OpStr, "INT_PTX_ATOM_CAS_32">;
2085+
defm _b64 : F_ATOMIC_3_INTRINSIC_PATTERN<I64RT, OpStr, "INT_PTX_ATOM_CAS_64">;
20902086
}
20912087

20922088
defm INT_PTX_SATOM_ADD : ATOM2_add_impl<"add">;

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