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| 1 | +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6 |
| 2 | +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.7-library -disable-llvm-passes -emit-llvm -finclude-default-header -o - %s | FileCheck %s |
| 3 | + |
| 4 | +// CHECK-LABEL: define hidden noundef <12 x i32> @_Z10trunc_castu11matrix_typeILm4ELm4EiE( |
| 5 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0:[0-9]+]] { |
| 6 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 7 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 8 | +// CHECK-NEXT: [[I34:%.*]] = alloca [12 x i32], align 4 |
| 9 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 10 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 11 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> |
| 12 | +// CHECK-NEXT: store <12 x i32> [[TRUNC]], ptr [[I34]], align 4 |
| 13 | +// CHECK-NEXT: [[TMP1:%.*]] = load <12 x i32>, ptr [[I34]], align 4 |
| 14 | +// CHECK-NEXT: ret <12 x i32> [[TMP1]] |
| 15 | +// |
| 16 | + int3x4 trunc_cast(int4x4 i44) { |
| 17 | + int3x4 i34 = i44; |
| 18 | + return i34; |
| 19 | +} |
| 20 | + |
| 21 | +// CHECK-LABEL: define hidden noundef <12 x i32> @_Z11trunc_cast0u11matrix_typeILm4ELm4EiE( |
| 22 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 23 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 24 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 25 | +// CHECK-NEXT: [[I43:%.*]] = alloca [12 x i32], align 4 |
| 26 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 27 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 28 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> |
| 29 | +// CHECK-NEXT: store <12 x i32> [[TRUNC]], ptr [[I43]], align 4 |
| 30 | +// CHECK-NEXT: [[TMP1:%.*]] = load <12 x i32>, ptr [[I43]], align 4 |
| 31 | +// CHECK-NEXT: ret <12 x i32> [[TMP1]] |
| 32 | +// |
| 33 | + int4x3 trunc_cast0(int4x4 i44) { |
| 34 | + int4x3 i43 = i44; |
| 35 | + return i43; |
| 36 | +} |
| 37 | + |
| 38 | +// CHECK-LABEL: define hidden noundef <9 x i32> @_Z11trunc_cast1u11matrix_typeILm4ELm4EiE( |
| 39 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 40 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 41 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 42 | +// CHECK-NEXT: [[I33:%.*]] = alloca [9 x i32], align 4 |
| 43 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 44 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 45 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> |
| 46 | +// CHECK-NEXT: store <9 x i32> [[TRUNC]], ptr [[I33]], align 4 |
| 47 | +// CHECK-NEXT: [[TMP1:%.*]] = load <9 x i32>, ptr [[I33]], align 4 |
| 48 | +// CHECK-NEXT: ret <9 x i32> [[TMP1]] |
| 49 | +// |
| 50 | + int3x3 trunc_cast1(int4x4 i44) { |
| 51 | + int3x3 i33 = i44; |
| 52 | + return i33; |
| 53 | +} |
| 54 | + |
| 55 | +// CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast2u11matrix_typeILm4ELm4EiE( |
| 56 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 57 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 58 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 59 | +// CHECK-NEXT: [[I32:%.*]] = alloca [6 x i32], align 4 |
| 60 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 61 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 62 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> |
| 63 | +// CHECK-NEXT: store <6 x i32> [[TRUNC]], ptr [[I32]], align 4 |
| 64 | +// CHECK-NEXT: [[TMP1:%.*]] = load <6 x i32>, ptr [[I32]], align 4 |
| 65 | +// CHECK-NEXT: ret <6 x i32> [[TMP1]] |
| 66 | +// |
| 67 | + int3x2 trunc_cast2(int4x4 i44) { |
| 68 | + int3x2 i32 = i44; |
| 69 | + return i32; |
| 70 | +} |
| 71 | + |
| 72 | +// CHECK-LABEL: define hidden noundef <6 x i32> @_Z11trunc_cast3u11matrix_typeILm4ELm4EiE( |
| 73 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 74 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 75 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 76 | +// CHECK-NEXT: [[I23:%.*]] = alloca [6 x i32], align 4 |
| 77 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 78 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 79 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> |
| 80 | +// CHECK-NEXT: store <6 x i32> [[TRUNC]], ptr [[I23]], align 4 |
| 81 | +// CHECK-NEXT: [[TMP1:%.*]] = load <6 x i32>, ptr [[I23]], align 4 |
| 82 | +// CHECK-NEXT: ret <6 x i32> [[TMP1]] |
| 83 | +// |
| 84 | + int2x3 trunc_cast3(int4x4 i44) { |
| 85 | + int2x3 i23 = i44; |
| 86 | + return i23; |
| 87 | +} |
| 88 | + |
| 89 | +// CHECK-LABEL: define hidden noundef <4 x i32> @_Z11trunc_cast4u11matrix_typeILm4ELm4EiE( |
| 90 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 91 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 92 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 93 | +// CHECK-NEXT: [[I22:%.*]] = alloca [4 x i32], align 4 |
| 94 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 95 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 96 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| 97 | +// CHECK-NEXT: store <4 x i32> [[TRUNC]], ptr [[I22]], align 4 |
| 98 | +// CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[I22]], align 4 |
| 99 | +// CHECK-NEXT: ret <4 x i32> [[TMP1]] |
| 100 | +// |
| 101 | + int2x2 trunc_cast4(int4x4 i44) { |
| 102 | + int2x2 i22 = i44; |
| 103 | + return i22; |
| 104 | +} |
| 105 | + |
| 106 | +// CHECK-LABEL: define hidden noundef <2 x i32> @_Z11trunc_cast5u11matrix_typeILm4ELm4EiE( |
| 107 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 108 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 109 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 110 | +// CHECK-NEXT: [[I21:%.*]] = alloca [2 x i32], align 4 |
| 111 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 112 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 113 | +// CHECK-NEXT: [[TRUNC:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32> poison, <2 x i32> <i32 0, i32 1> |
| 114 | +// CHECK-NEXT: store <2 x i32> [[TRUNC]], ptr [[I21]], align 4 |
| 115 | +// CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[I21]], align 4 |
| 116 | +// CHECK-NEXT: ret <2 x i32> [[TMP1]] |
| 117 | +// |
| 118 | + int2x1 trunc_cast5(int4x4 i44) { |
| 119 | + int2x1 i21 = i44; |
| 120 | + return i21; |
| 121 | +} |
| 122 | + |
| 123 | +// CHECK-LABEL: define hidden noundef i32 @_Z11trunc_cast6u11matrix_typeILm4ELm4EiE( |
| 124 | +// CHECK-SAME: <16 x i32> noundef [[I44:%.*]]) #[[ATTR0]] { |
| 125 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 126 | +// CHECK-NEXT: [[I44_ADDR:%.*]] = alloca [16 x i32], align 4 |
| 127 | +// CHECK-NEXT: [[I1:%.*]] = alloca i32, align 4 |
| 128 | +// CHECK-NEXT: store <16 x i32> [[I44]], ptr [[I44_ADDR]], align 4 |
| 129 | +// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[I44_ADDR]], align 4 |
| 130 | +// CHECK-NEXT: [[CAST_MTRUNC:%.*]] = extractelement <16 x i32> [[TMP0]], i32 0 |
| 131 | +// CHECK-NEXT: store i32 [[CAST_MTRUNC]], ptr [[I1]], align 4 |
| 132 | +// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I1]], align 4 |
| 133 | +// CHECK-NEXT: ret i32 [[TMP1]] |
| 134 | +// |
| 135 | + int trunc_cast6(int4x4 i44) { |
| 136 | + int i1 = i44; |
| 137 | + return i1; |
| 138 | +} |
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