We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent d743616 commit ad6e9f9Copy full SHA for ad6e9f9
llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
@@ -45,6 +45,12 @@ tablegen("MipsGenRegisterBank") {
45
td_file = "Mips.td"
46
}
47
48
+tablegen("MipsGenSDNodeInfo") {
49
+ visibility = [ ":LLVMMipsCodeGen" ]
50
+ args = [ "-gen-sd-node-info" ]
51
+ td_file = "Mips.td"
52
+}
53
+
54
static_library("LLVMMipsCodeGen") {
55
deps = [
56
":MipsGenCallingConv",
@@ -54,6 +60,7 @@ static_library("LLVMMipsCodeGen") {
60
":MipsGenMCPseudoLowering",
61
":MipsGenPostLegalizeGICombiner",
62
":MipsGenRegisterBank",
63
+ ":MipsGenSDNodeInfo",
57
64
"MCTargetDesc",
58
65
"TargetInfo",
59
66
"//llvm/include/llvm/Config:llvm-config",
0 commit comments