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Fix bitwise and error
1 parent 81958ac commit ad701bb

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llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -868,7 +868,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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break;
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TypeSize DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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TypeSize SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, TRI);
871-
if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &
871+
if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&
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all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
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[&](const MachineInstr &UseMI) {
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return onlyUsesFP(UseMI, MRI, TRI) ||
@@ -1172,7 +1172,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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}
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TypeSize DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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TypeSize SrcSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, TRI);
1175-
if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &
1175+
if (((DstSize == SrcSize) || STI.hasFeature(AArch64::FeatureFPRCVT)) &&
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all_of(MRI.use_nodbg_instructions(MI.getOperand(0).getReg()),
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[&](const MachineInstr &UseMI) {
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return onlyUsesFP(UseMI, MRI, TRI) ||

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