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[AggressiveInstCombine] Address review comments. NFC.
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2 files changed

+7
-7
lines changed

2 files changed

+7
-7
lines changed

llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -681,7 +681,7 @@ static bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
681681
if (Load1Ptr != Load2Ptr)
682682
return false;
683683

684-
// Support Loadsizes that equal to the corresponding store sizes.
684+
// Make sure that there are no padding bits.
685685
if (!DL.typeSizeEqualsStoreSize(LI1->getType()) || !DL.typeSizeEqualsStoreSize(LI2->getType()))
686686
return false;
687687

llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1813,7 +1813,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size(ptr %p) {
18131813

18141814
define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size2(ptr %p) {
18151815
; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size2(
1816-
; ALL-NEXT: [[P1:%.*]] = getelementptr i4, ptr [[P:%.*]], i32 7
1816+
; ALL-NEXT: [[P1:%.*]] = getelementptr i28, ptr [[P:%.*]], i32 1
18171817
; ALL-NEXT: [[L1:%.*]] = load i28, ptr [[P]], align 4
18181818
; ALL-NEXT: [[L2:%.*]] = load i4, ptr [[P1]], align 1
18191819
; ALL-NEXT: [[E1:%.*]] = zext i28 [[L1]] to i32
@@ -1822,7 +1822,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size2(ptr %p) {
18221822
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
18231823
; ALL-NEXT: ret i32 [[O1]]
18241824
;
1825-
%p1 = getelementptr i4, ptr %p, i32 7
1825+
%p1 = getelementptr i28, ptr %p, i32 1
18261826
%l1 = load i28, ptr %p
18271827
%l2 = load i4, ptr %p1
18281828
%e1 = zext i28 %l1 to i32
@@ -1834,7 +1834,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size2(ptr %p) {
18341834

18351835
define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size3(ptr %p) {
18361836
; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size3(
1837-
; ALL-NEXT: [[P1:%.*]] = getelementptr i1, ptr [[P:%.*]], i32 23
1837+
; ALL-NEXT: [[P1:%.*]] = getelementptr i23, ptr [[P:%.*]], i32 1
18381838
; ALL-NEXT: [[L1:%.*]] = load i23, ptr [[P]], align 4
18391839
; ALL-NEXT: [[L2:%.*]] = load i9, ptr [[P1]], align 2
18401840
; ALL-NEXT: [[E1:%.*]] = zext i23 [[L1]] to i32
@@ -1843,7 +1843,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size3(ptr %p) {
18431843
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
18441844
; ALL-NEXT: ret i32 [[O1]]
18451845
;
1846-
%p1 = getelementptr i1, ptr %p, i32 23
1846+
%p1 = getelementptr i23, ptr %p, i32 1
18471847
%l1 = load i23, ptr %p
18481848
%l2 = load i9, ptr %p1
18491849
%e1 = zext i23 %l1 to i32
@@ -1855,7 +1855,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size3(ptr %p) {
18551855

18561856
define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size4(ptr %p) {
18571857
; ALL-LABEL: @loadCombine_2consecutive_mixsize_not_equal_store_size4(
1858-
; ALL-NEXT: [[P1:%.*]] = getelementptr i1, ptr [[P:%.*]], i32 9
1858+
; ALL-NEXT: [[P1:%.*]] = getelementptr i9, ptr [[P:%.*]], i32 1
18591859
; ALL-NEXT: [[L1:%.*]] = load i9, ptr [[P]], align 2
18601860
; ALL-NEXT: [[L2:%.*]] = load i23, ptr [[P1]], align 4
18611861
; ALL-NEXT: [[E1:%.*]] = zext i9 [[L1]] to i32
@@ -1864,7 +1864,7 @@ define i32 @loadCombine_2consecutive_mixsize_not_equal_store_size4(ptr %p) {
18641864
; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
18651865
; ALL-NEXT: ret i32 [[O1]]
18661866
;
1867-
%p1 = getelementptr i1, ptr %p, i32 9
1867+
%p1 = getelementptr i9, ptr %p, i32 1
18681868
%l1 = load i9, ptr %p
18691869
%l2 = load i23, ptr %p1
18701870
%e1 = zext i9 %l1 to i32

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