fixup! Update comment about EMUL of mask-producing instructions

mshockwave · mshockwave · commit ad8229b9d2c7 · 2025-03-17T11:18:34.000-07:00
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -396,7 +396,7 @@ foreach mx = SchedMxList in {
       defm "" : LMULWriteResMX<"WriteVSTE",  [SiFiveP400VST], mx, IsWorstCase>;
     }
 
-    // Mask load and store always have EMUL=1.
+    // Mask load and store have a maximum EMUL of 1.
     let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in {
       defm "" : LMULWriteResMX<"WriteVLDM",  [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>;
       defm "" : LMULWriteResMX<"WriteVSTM",  [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -572,7 +572,7 @@ foreach mx = SchedMxList in {
       defm "" : LMULWriteResMX<"WriteVSTE",  [SiFiveP600VST], mx, IsWorstCase>;
     }
 
-    // Mask load and store always have EMUL=1.
+    // Mask load and store have a maximum EMUL of 1.
     let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in {
       defm "" : LMULWriteResMX<"WriteVLDM",  [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>;
       defm "" : LMULWriteResMX<"WriteVSTM",  [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>;

Original file line number	Diff line number	Diff line change
`@@ -396,7 +396,7 @@ foreach mx = SchedMxList in {`
`396`	`396`	`defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;`
`397`	`397`	`}`
`398`	`398`
`399`		`- // Mask load and store always have EMUL=1.`
	`399`	`+ // Mask load and store have a maximum EMUL of 1.`
`400`	`400`	`let ReleaseAtCycles = [SiFiveP400GetLMulCycles<"M1">.c] in {`
`401`	`401`	`defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase=!eq(mx, "M1")>;`
`402`	`402`	`defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase=!eq(mx, "M1")>;`
Original file line number	Diff line number	Diff line change
`@@ -572,7 +572,7 @@ foreach mx = SchedMxList in {`
`572`	`572`	`defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP600VST], mx, IsWorstCase>;`
`573`	`573`	`}`
`574`	`574`
`575`		`- // Mask load and store always have EMUL=1.`
	`575`	`+ // Mask load and store have a maximum EMUL of 1.`
`576`	`576`	`let ReleaseAtCycles = [SiFiveP600GetLMulCycles<"M1">.c] in {`
`577`	`577`	`defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP600VLD], mx, IsWorstCase=!eq(mx,"M1")>;`
`578`	`578`	`defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP600VST], mx, IsWorstCase=!eq(mx,"M1")>;`