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farzonlfarzonl
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[NFC][SPIRV] Fix for selectExtInst to be able to process intrinsics (#110864)
`selectExtInst` tries to add the intrinsic to the SPIRV GL extension instruction. `MO_IntrinsicID` is always the first operand when we come from `selectIntrinsic`. For all those cases `selectExtInst` needs to know to start at index 2.
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‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp‎

Lines changed: 13 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -151,18 +151,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
151151
bool selectFCmp(Register ResVReg, const SPIRVType *ResType,
152152
MachineInstr &I) const;
153153

154-
bool selectFmix(Register ResVReg, const SPIRVType *ResType,
155-
MachineInstr &I) const;
156-
157-
bool selectLength(Register ResVReg, const SPIRVType *ResType,
158-
MachineInstr &I) const;
159-
160-
bool selectFrac(Register ResVReg, const SPIRVType *ResType,
161-
MachineInstr &I) const;
162-
163-
bool selectRsqrt(Register ResVReg, const SPIRVType *ResType,
164-
MachineInstr &I) const;
165-
166154
bool selectSign(Register ResVReg, const SPIRVType *ResType,
167155
MachineInstr &I) const;
168156

@@ -235,18 +223,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
235223
bool selectLog10(Register ResVReg, const SPIRVType *ResType,
236224
MachineInstr &I) const;
237225

238-
bool selectNormalize(Register ResVReg, const SPIRVType *ResType,
239-
MachineInstr &I) const;
240-
241226
bool selectSaturate(Register ResVReg, const SPIRVType *ResType,
242227
MachineInstr &I) const;
243228

244229
bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
245230
MachineInstr &I) const;
246231

247-
bool selectStep(Register ResVReg, const SPIRVType *ResType,
248-
MachineInstr &I) const;
249-
250232
bool selectUnmergeValues(MachineInstr &I) const;
251233

252234
// Utilities
@@ -802,8 +784,13 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
802784
.addImm(static_cast<uint32_t>(Set))
803785
.addImm(Opcode);
804786
const unsigned NumOps = I.getNumOperands();
805-
for (unsigned i = 1; i < NumOps; ++i)
806-
MIB.add(I.getOperand(i));
787+
unsigned Index = 1;
788+
if (Index < NumOps &&
789+
I.getOperand(Index).getType() ==
790+
MachineOperand::MachineOperandType::MO_IntrinsicID)
791+
Index = 2;
792+
for (; Index < NumOps; ++Index)
793+
MIB.add(I.getOperand(Index));
807794
return MIB.constrainAllUses(TII, TRI, RBI);
808795
}
809796
}
@@ -1605,95 +1592,6 @@ bool SPIRVInstructionSelector::selectAny(Register ResVReg,
16051592
return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
16061593
}
16071594

1608-
bool SPIRVInstructionSelector::selectFmix(Register ResVReg,
1609-
const SPIRVType *ResType,
1610-
MachineInstr &I) const {
1611-
1612-
assert(I.getNumOperands() == 5);
1613-
assert(I.getOperand(2).isReg());
1614-
assert(I.getOperand(3).isReg());
1615-
assert(I.getOperand(4).isReg());
1616-
MachineBasicBlock &BB = *I.getParent();
1617-
1618-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1619-
.addDef(ResVReg)
1620-
.addUse(GR.getSPIRVTypeID(ResType))
1621-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1622-
.addImm(GL::FMix)
1623-
.addUse(I.getOperand(2).getReg())
1624-
.addUse(I.getOperand(3).getReg())
1625-
.addUse(I.getOperand(4).getReg())
1626-
.constrainAllUses(TII, TRI, RBI);
1627-
}
1628-
1629-
bool SPIRVInstructionSelector::selectLength(Register ResVReg,
1630-
const SPIRVType *ResType,
1631-
MachineInstr &I) const {
1632-
1633-
assert(I.getNumOperands() == 3);
1634-
assert(I.getOperand(2).isReg());
1635-
MachineBasicBlock &BB = *I.getParent();
1636-
1637-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1638-
.addDef(ResVReg)
1639-
.addUse(GR.getSPIRVTypeID(ResType))
1640-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1641-
.addImm(GL::Length)
1642-
.addUse(I.getOperand(2).getReg())
1643-
.constrainAllUses(TII, TRI, RBI);
1644-
}
1645-
1646-
bool SPIRVInstructionSelector::selectFrac(Register ResVReg,
1647-
const SPIRVType *ResType,
1648-
MachineInstr &I) const {
1649-
1650-
assert(I.getNumOperands() == 3);
1651-
assert(I.getOperand(2).isReg());
1652-
MachineBasicBlock &BB = *I.getParent();
1653-
1654-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1655-
.addDef(ResVReg)
1656-
.addUse(GR.getSPIRVTypeID(ResType))
1657-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1658-
.addImm(GL::Fract)
1659-
.addUse(I.getOperand(2).getReg())
1660-
.constrainAllUses(TII, TRI, RBI);
1661-
}
1662-
1663-
bool SPIRVInstructionSelector::selectNormalize(Register ResVReg,
1664-
const SPIRVType *ResType,
1665-
MachineInstr &I) const {
1666-
1667-
assert(I.getNumOperands() == 3);
1668-
assert(I.getOperand(2).isReg());
1669-
MachineBasicBlock &BB = *I.getParent();
1670-
1671-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1672-
.addDef(ResVReg)
1673-
.addUse(GR.getSPIRVTypeID(ResType))
1674-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1675-
.addImm(GL::Normalize)
1676-
.addUse(I.getOperand(2).getReg())
1677-
.constrainAllUses(TII, TRI, RBI);
1678-
}
1679-
1680-
bool SPIRVInstructionSelector::selectRsqrt(Register ResVReg,
1681-
const SPIRVType *ResType,
1682-
MachineInstr &I) const {
1683-
1684-
assert(I.getNumOperands() == 3);
1685-
assert(I.getOperand(2).isReg());
1686-
MachineBasicBlock &BB = *I.getParent();
1687-
1688-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1689-
.addDef(ResVReg)
1690-
.addUse(GR.getSPIRVTypeID(ResType))
1691-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1692-
.addImm(GL::InverseSqrt)
1693-
.addUse(I.getOperand(2).getReg())
1694-
.constrainAllUses(TII, TRI, RBI);
1695-
}
1696-
16971595
// Select the OpDot instruction for the given float dot
16981596
bool SPIRVInstructionSelector::selectFloatDot(Register ResVReg,
16991597
const SPIRVType *ResType,
@@ -1853,25 +1751,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
18531751
return Result;
18541752
}
18551753

1856-
bool SPIRVInstructionSelector::selectStep(Register ResVReg,
1857-
const SPIRVType *ResType,
1858-
MachineInstr &I) const {
1859-
1860-
assert(I.getNumOperands() == 4);
1861-
assert(I.getOperand(2).isReg());
1862-
assert(I.getOperand(3).isReg());
1863-
MachineBasicBlock &BB = *I.getParent();
1864-
1865-
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
1866-
.addDef(ResVReg)
1867-
.addUse(GR.getSPIRVTypeID(ResType))
1868-
.addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450))
1869-
.addImm(GL::Step)
1870-
.addUse(I.getOperand(2).getReg())
1871-
.addUse(I.getOperand(3).getReg())
1872-
.constrainAllUses(TII, TRI, RBI);
1873-
}
1874-
18751754
bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
18761755
const SPIRVType *ResType,
18771756
MachineInstr &I) const {
@@ -2622,15 +2501,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
26222501
case Intrinsic::spv_any:
26232502
return selectAny(ResVReg, ResType, I);
26242503
case Intrinsic::spv_lerp:
2625-
return selectFmix(ResVReg, ResType, I);
2504+
return selectExtInst(ResVReg, ResType, I, CL::mix, GL::FMix);
26262505
case Intrinsic::spv_length:
2627-
return selectLength(ResVReg, ResType, I);
2506+
return selectExtInst(ResVReg, ResType, I, CL::length, GL::Length);
26282507
case Intrinsic::spv_frac:
2629-
return selectFrac(ResVReg, ResType, I);
2508+
return selectExtInst(ResVReg, ResType, I, CL::fract, GL::Fract);
26302509
case Intrinsic::spv_normalize:
2631-
return selectNormalize(ResVReg, ResType, I);
2510+
return selectExtInst(ResVReg, ResType, I, CL::normalize, GL::Normalize);
26322511
case Intrinsic::spv_rsqrt:
2633-
return selectRsqrt(ResVReg, ResType, I);
2512+
return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt);
26342513
case Intrinsic::spv_sign:
26352514
return selectSign(ResVReg, ResType, I);
26362515
case Intrinsic::spv_lifetime_start:
@@ -2654,7 +2533,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
26542533
.addUse(GR.getOrCreateConstInt(3, I, IntTy, TII));
26552534
}
26562535
case Intrinsic::spv_step:
2657-
return selectStep(ResVReg, ResType, I);
2536+
return selectExtInst(ResVReg, ResType, I, CL::step, GL::Step);
26582537
// Discard intrinsics which we do not expect to actually represent code after
26592538
// lowering or intrinsics which are not implemented but should not crash when
26602539
// found in a customer's LLVM IR input.

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