Wait with FCOPYSIGN optimization.

Author: JonPsson1

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

@@ -553,7 +553,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, LibCall);
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
     setOperationAction(ISD::IS_FPCLASS, MVT::f16, Custom);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
+    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Legal);
   }
 
   for (unsigned I = MVT::FIRST_FP_VALUETYPE;
@@ -6989,21 +6989,6 @@ SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op,
   return getCCResult(DAG, Intr);
 }
 
-SDValue SystemZTargetLowering::lowerFCOPYSIGN(SDValue Op,
-                                              SelectionDAG &DAG) const {
-  MVT VT = Op.getSimpleValueType();
-  SDValue ValOp = Op.getOperand(0);
-  SDValue SignOp = Op.getOperand(1);
-
-  // Remove the rounding which would result in a libcall for half.
-  if (VT == MVT::f16 && SignOp.getOpcode() == ISD::FP_ROUND) {
-    SDValue WideOp = SignOp.getOperand(0);
-    return DAG.getNode(ISD::FCOPYSIGN, SDLoc(Op), VT, ValOp, WideOp);
-  }
-
-  return Op; // Legal
-}
-
 SDValue SystemZTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
@@ -7175,8 +7160,6 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
     return lowerStoreF16(Op, DAG);
   case ISD::IS_FPCLASS:
     return lowerIS_FPCLASS(Op, DAG);
-  case ISD::FCOPYSIGN:
-    return lowerFCOPYSIGN(Op, DAG);
   case ISD::GET_ROUNDING:
     return lowerGET_ROUNDING(Op, DAG);
   case ISD::READCYCLECOUNTER:

llvm/lib/Target/SystemZ/SystemZISelLowering.h

@@ -755,7 +755,6 @@ class SystemZTargetLowering : public TargetLowering {
   SDValue lowerStoreF16(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue lowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
-  SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
 

llvm/test/CodeGen/SystemZ/fp-copysign-03.ll

@@ -43,18 +43,46 @@ define half @f2(half %a, double %b) {
 }
 
 ; Test copysign with an f16 result and f128 sign argument.
+; TODO: Let the DAGCombiner remove the fp_round.
 define half @f3(half %a, fp128 %b) {
 ; Z10-LABEL: f3:
 ; Z10:       # %bb.0:
+; Z10-NEXT:    stmg %r14, %r15, 112(%r15)
+; Z10-NEXT:    .cfi_offset %r14, -48
+; Z10-NEXT:    .cfi_offset %r15, -40
+; Z10-NEXT:    aghi %r15, -184
+; Z10-NEXT:    .cfi_def_cfa_offset 344
+; Z10-NEXT:    std %f8, 176(%r15) # 8-byte Spill
+; Z10-NEXT:    .cfi_offset %f8, -168
 ; Z10-NEXT:    ld %f1, 0(%r2)
 ; Z10-NEXT:    ld %f3, 8(%r2)
-; Z10-NEXT:    cpsdr %f0, %f1, %f0
+; Z10-NEXT:    ler %f8, %f0
+; Z10-NEXT:    la %r2, 160(%r15)
+; Z10-NEXT:    std %f1, 160(%r15)
+; Z10-NEXT:    std %f3, 168(%r15)
+; Z10-NEXT:    brasl %r14, __trunctfhf2@PLT
+; Z10-NEXT:    cpsdr %f0, %f0, %f8
+; Z10-NEXT:    ld %f8, 176(%r15) # 8-byte Reload
+; Z10-NEXT:    lmg %r14, %r15, 296(%r15)
 ; Z10-NEXT:    br %r14
 ;
 ; Z16-LABEL: f3:
 ; Z16:       # %bb.0:
-; Z16-NEXT:    vl %v1, 0(%r2), 3
-; Z16-NEXT:    cpsdr %f0, %f1, %f0
+; Z16-NEXT:    stmg %r14, %r15, 112(%r15)
+; Z16-NEXT:    .cfi_offset %r14, -48
+; Z16-NEXT:    .cfi_offset %r15, -40
+; Z16-NEXT:    aghi %r15, -184
+; Z16-NEXT:    .cfi_def_cfa_offset 344
+; Z16-NEXT:    std %f8, 176(%r15) # 8-byte Spill
+; Z16-NEXT:    .cfi_offset %f8, -168
+; Z16-NEXT:    ldr %f8, %f0
+; Z16-NEXT:    vl %v0, 0(%r2), 3
+; Z16-NEXT:    la %r2, 160(%r15)
+; Z16-NEXT:    vst %v0, 160(%r15), 3
+; Z16-NEXT:    brasl %r14, __trunctfhf2@PLT
+; Z16-NEXT:    cpsdr %f0, %f0, %f8
+; Z16-NEXT:    ld %f8, 176(%r15) # 8-byte Reload
+; Z16-NEXT:    lmg %r14, %r15, 296(%r15)
 ; Z16-NEXT:    br %r14
   %bh = fptrunc fp128 %b to half
   %res = call half @llvm.copysign.f16(half %a, half %bh)