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Merge branch 'main' into users/kasuga-fj/da-gcdmiv-remove-special-handling
2 parents 6b3d008 + 4978cd3 commit ae56169

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7 files changed

+58
-7
lines changed

7 files changed

+58
-7
lines changed

llvm/lib/Analysis/DependenceAnalysis.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2582,7 +2582,9 @@ bool DependenceInfo::gcdMIVtest(const SCEV *Src, const SCEV *Dst,
25822582
const SCEV *DstConst = Coefficients;
25832583

25842584
APInt ExtraGCD = APInt::getZero(BitWidth);
2585-
const SCEV *Delta = SE->getMinusSCEV(DstConst, SrcConst);
2585+
const SCEV *Delta = minusSCEVNoSignedOverflow(DstConst, SrcConst, *SE);
2586+
if (!Delta)
2587+
return false;
25862588
LLVM_DEBUG(dbgs() << " Delta = " << *Delta << "\n");
25872589
const SCEVConstant *Constant = dyn_cast<SCEVConstant>(Delta);
25882590
if (!Constant)

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -530,7 +530,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
530530

531531
setOperationAction(ISD::FREM, MVT::f32, Expand);
532532
setOperationAction(ISD::FREM, MVT::f64, Expand);
533-
setOperationAction(ISD::FREM, MVT::f80, Expand);
534533

535534
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
536535

llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,7 @@ define void @gcdmiv_delta_ovfl(ptr %A) {
8989
; CHECK-GCD-MIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 0, ptr %idx.0, align 1
9090
; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]!
9191
; CHECK-GCD-MIV-NEXT: Src: store i8 0, ptr %idx.0, align 1 --> Dst: store i8 1, ptr %idx.1, align 1
92-
; CHECK-GCD-MIV-NEXT: da analyze - none!
92+
; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*|<]!
9393
; CHECK-GCD-MIV-NEXT: Src: store i8 1, ptr %idx.1, align 1 --> Dst: store i8 1, ptr %idx.1, align 1
9494
; CHECK-GCD-MIV-NEXT: da analyze - consistent output [*]!
9595
;

llvm/utils/gn/secondary/bolt/unittests/BUILD.gn

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ group("unittests") {
22
deps = [
33
"Core:CoreTests",
44
"Profile:ProfileTests",
5+
"Passes:PassTests",
56
]
67
testonly = true
78
}
Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
import("//llvm/lib/Target/targets.gni")
2+
import("//third-party/unittest/unittest.gni")
3+
4+
unittest("PassTests") {
5+
configs += [ "//llvm/utils/gn/build:bolt_code" ]
6+
deps = [
7+
"//bolt/include/bolt/Core:TargetConfig.def",
8+
"//bolt/lib/Core",
9+
"//bolt/lib/Passes",
10+
"//bolt/lib/Profile",
11+
"//bolt/lib/Rewrite",
12+
"//bolt/lib/Utils",
13+
"//llvm/lib/DebugInfo/DWARF",
14+
"//llvm/lib/MC",
15+
"//llvm/lib/Object",
16+
"//llvm/lib/Target:TargetsToBuild",
17+
]
18+
sources = [ "InsertNegateRAState.cpp" ]
19+
20+
defines = []
21+
include_dirs = []
22+
if (llvm_build_AArch64) {
23+
defines += [ "AARCH64_AVAILABLE" ]
24+
25+
# This target reaches into the internal headers of LLVM's AArch64 library.
26+
# That target doesn't expect that, so it doesn't use public_deps for
27+
# tblgen-generated headers used only in internal headers (...which this
28+
# target here questionably includes). So depend on the target that generates
29+
# those headers here.
30+
include_dirs += [ "//llvm/lib/Target/AArch64" ]
31+
deps += [
32+
"//llvm/lib/Target/AArch64:AArch64GenSDNodeInfo",
33+
"//llvm/lib/Target/AArch64/MCTargetDesc",
34+
"//llvm/lib/Target/AArch64/Utils",
35+
]
36+
}
37+
if (llvm_build_X86) {
38+
defines += [ "X86_AVAILABLE" ]
39+
40+
# This target reaches into the internal headers of LLVM's X86 library.
41+
# That target doesn't expect that, so it doesn't use public_deps for
42+
# tblgen-generated headers used only in internal headers (...which this
43+
# target here questionably includes). So depend on the target that generates
44+
# those headers here.
45+
include_dirs += [ "//llvm/lib/Target/X86" ]
46+
deps += [ "//llvm/lib/Target/X86/MCTargetDesc" ]
47+
}
48+
}

llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ tablegen("AArch64GenSDNodeInfo") {
7676
visibility = [
7777
":LLVMAArch64CodeGen",
7878
"//bolt/unittests/Core:CoreTests",
79+
"//bolt/unittests/Passes:PassTests",
7980
"//llvm/unittests/Target/AArch64:AArch64Tests",
8081
]
8182
args = [ "-gen-sd-node-info" ]

mlir/test/Integration/Dialect/Linalg/CPU/runtime-verification.mlir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,10 +80,10 @@ func.func @main() {
8080
%c64x57 = arith.constant dense<0.0> : tensor<16x29xf32>
8181
%c3x4 = arith.constant dense<0.0> : tensor<3x4xf32>
8282

83-
// TODO: BROKEN CHK: ERROR: Runtime op verification failed
84-
// TODO: BROKEN CHK-NEXT: linalg.generic
85-
// TODO: BROKEN CHK-NEXT: unexpected negative result on dimension #0 of input/output operand #0
86-
// TODO: BROKEN func.call @reverse_from_3(%d5x) : (tensor<?xf32>) -> (tensor<?xf32>)
83+
// CHECK: ERROR: Runtime op verification failed
84+
// CHECK-NEXT: linalg.generic
85+
// CHECK-NEXT: unexpected negative result on dimension #0 of input/output operand #0
86+
func.call @reverse_from_3(%d5x) : (tensor<?xf32>) -> (tensor<?xf32>)
8787

8888
%c0x = arith.constant dense<1.0> : tensor<0xf32>
8989
%d0x = tensor.cast %c0x : tensor<0xf32> to tensor<?xf32>

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