Use ZPR_K register class in Decoder method

Author: SpencerAbson

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

@@ -394,14 +394,11 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
 // 111
 static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
                              const MCDisassembler *Decoder) {
-  // RegNo <  4 => Reg is in Z20-Z23 (offset 20)
-  // RegNo >= 4 => Reg is in Z28-Z31 (offset 24)
-  unsigned Reg = (RegNo < 4) ? (RegNo + 20) : (RegNo + 24);
-  if (!(Reg >= 20 && Reg <= 23) && !(Reg >= 28 && Reg <= 31))
+  if (RegNo > 7)
     return Fail;
 
   unsigned Register =
-      AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
+      AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

@@ -584,10 +584,14 @@ uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,
                                         const MCSubtargetInfo &STI) const {
   auto RegOpnd = MI.getOperand(OpIdx).getReg();
   unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
-  // Z28 => RegVal = 28 (28 - 24 = 4) Z28 = 4
+
+  // ZZ8-Z31 => Reg is in 3..7 (offset 24)
   if (RegOpnd > AArch64::Z27)
     return (RegVal - 24);
-  // Z20 => RegVal = 20 (20 -20 = 0) Z20 = 0
+
+  assert((RegOpnd > AArch64::Z19 && RegOpnd < AArch64::Z24) &&
+         "Expected ZK in Z20..Z23 or Z28..Z31");
+  // Z20-Z23 => Reg is in 0..3 (offset 20)
   return (RegVal - 20);
 }