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[AArch64] Add assembly/disassembly for SVE_AES2 multi-vector instructions
- Add assembly/disassembly for the following instructions - AESE (two/four, four registers) - AESD (two/four, four registers) - AESDIMC (two/four registers) - AESEMC (two/four registers) - Introduce assembler extension tests for the new Armv9.6 sve-aes2 and ssve-aes features - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
1 parent c0c36aa commit ae8f86f

19 files changed

+654
-6
lines changed

‎llvm/lib/Target/AArch64/AArch64.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ def SVEUnsupported : AArch64Unsupported {
7373
SVE2Unsupported.F);
7474
}
7575

76-
let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1] in
76+
let F = [HasSME2p1, HasSVE2p1_or_HasSME2p1, HasSVE2p1orSSVE_AES] in
7777
def SME2p1Unsupported : AArch64Unsupported;
7878

7979
def SME2Unsupported : AArch64Unsupported {

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3917,6 +3917,19 @@ let Predicates = [HasSVE2BitPerm] in {
39173917
defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp", int_aarch64_sve_bgrp_x>;
39183918
} // End HasSVE2BitPerm
39193919

3920+
let Predicates = [HasSVEAES2, HasSVE2p1orSSVE_AES] in {
3921+
// SVE_AES2 multi-vector instructions (x2)
3922+
def AESE_2ZZI_B : sve_crypto_binary_multi2<0b000, "aese">;
3923+
def AESD_2ZZI_B : sve_crypto_binary_multi2<0b010, "aesd">;
3924+
def AESEMC_2ZZI_B : sve_crypto_binary_multi2<0b100, "aesemc">;
3925+
def AESDMIC_2ZZI_B : sve_crypto_binary_multi2<0b110, "aesdimc">;
3926+
// SVE_AES2 multi-vector instructions (x4)
3927+
def AESE_4ZZI_B : sve_crypto_binary_multi4<0b0000, "aese">;
3928+
def AESD_4ZZI_B : sve_crypto_binary_multi4<0b0100, "aesd">;
3929+
def AESEMC_4ZZI_B : sve_crypto_binary_multi4<0b1000, "aesemc">;
3930+
def AESDMIC_4ZZI_B : sve_crypto_binary_multi4<0b1100, "aesdimc">;
3931+
} // End HasSVEAES2, HasSVE2p1orSSVE_AES
3932+
39203933
//===----------------------------------------------------------------------===//
39213934
// SME or SVE2.1 instructions
39223935
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8698,6 +8698,54 @@ multiclass sve2_crypto_unary_op<bit opc, string asm, SDPatternOperator op> {
86988698
def : SVE_1_Op_Pat<nxv16i8, op, nxv16i8, !cast<Instruction>(NAME)>;
86998699
}
87008700

8701+
class sve_crypto_binary_multi2<bits<3> opc, string asm>
8702+
: I<(outs ZZ_b_mul_r:$Zdn),
8703+
(ins ZZ_b_mul_r:$_Zdn, ZPR128:$Zm, VectorIndexS32b_timm:$imm2),
8704+
asm,
8705+
"\t$Zdn, $_Zdn, $Zm$imm2",
8706+
"",
8707+
[]>, Sched<[]> {
8708+
bits<5> Zm;
8709+
bits<4> Zdn;
8710+
bits<2> imm2;
8711+
let Inst{31-21} = 0b01000101001;
8712+
let Inst{20-19} = imm2;
8713+
let Inst{18-17} = 0b01;
8714+
let Inst{16} = opc{2};
8715+
let Inst{15-11} = 0b11101;
8716+
let Inst{10} = opc{1};
8717+
let Inst{9-5} = Zm;
8718+
let Inst{4-1} = Zdn;
8719+
let Inst{0} = opc{0};
8720+
8721+
let Constraints = "$Zdn = $_Zdn";
8722+
let hasSideEffects = 0;
8723+
}
8724+
8725+
class sve_crypto_binary_multi4<bits<4> opc, string asm>
8726+
: I<(outs ZZZZ_b_mul_r:$Zdn),
8727+
(ins ZZZZ_b_mul_r:$_Zdn, ZPR128:$Zm, VectorIndexS32b_timm:$imm2),
8728+
asm,
8729+
"\t$Zdn, $_Zdn, $Zm$imm2",
8730+
"",
8731+
[]>, Sched<[]> {
8732+
bits<5> Zm;
8733+
bits<3> Zdn;
8734+
bits<2> imm2;
8735+
let Inst{31-21} = 0b01000101001;
8736+
let Inst{20-19} = imm2;
8737+
let Inst{18-17} = 0b11;
8738+
let Inst{16} = opc{3};
8739+
let Inst{15-11} = 0b11101;
8740+
let Inst{10} = opc{2};
8741+
let Inst{9-5} = Zm;
8742+
let Inst{4-2} = Zdn;
8743+
let Inst{1-0} = opc{1-0};
8744+
8745+
let Constraints = "$Zdn = $_Zdn";
8746+
let hasSideEffects = 0;
8747+
}
8748+
87018749
//===----------------------------------------------------------------------===//
87028750
// SVE BFloat16 Group
87038751
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,3 +17,9 @@ bfclamp { z0.h, z1.h }, z0.h, z0.h
1717
bfadd za.h[w8, 3], {z20.h-z21.h}
1818
// CHECK: error: instruction requires: sme-b16b16
1919
// CHECK: bfadd za.h[w8, 3], {z20.h-z21.h}
20+
21+
.arch armv9-a+sve-aes2+ssve-aes
22+
.arch armv9-a+nossve-aes
23+
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
24+
// CHECK: error: instruction requires: sve2p1 or ssve-aes sve-aes2
25+
// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]

‎llvm/test/MC/AArch64/SME2p1/directive-arch.s‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,3 +8,7 @@ sqcvt z0.h, {z0.s, z1.s}
88
.arch armv9-a+sme2+sve-b16b16
99
bfclamp { z0.h, z1.h }, z0.h, z0.h
1010
// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
11+
12+
.arch armv9-a+sve-aes2+ssve-aes
13+
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
14+
// CHECK: aesdimc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]

‎llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,4 +17,11 @@ bfclamp { z0.h, z1.h }, z0.h, z0.h
1717
.arch_extension nosme-b16b16
1818
bfadd za.h[w8, 3], {z20.h-z21.h}
1919
// CHECK: error: instruction requires: sme-b16b16
20-
// CHECK: bfadd za.h[w8, 3], {z20.h-z21.h}
20+
// CHECK: bfadd za.h[w8, 3], {z20.h-z21.h}
21+
22+
.arch_extension sve-aes2
23+
.arch_extension ssve-aes
24+
.arch_extension nossve-aes
25+
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
26+
// CHECK: error: instruction requires: sve2p1 or ssve-aes
27+
// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]

‎llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,4 +11,9 @@ bfclamp { z0.h, z1.h }, z0.h, z0.h
1111

1212
.arch_extension sme-b16b16
1313
bfadd za.h[w8, 3], {z20.h-z21.h}
14-
// CHECK: bfadd za.h[w8, 3, vgx2], { z20.h, z21.h }
14+
// CHECK: bfadd za.h[w8, 3, vgx2], { z20.h, z21.h }
15+
16+
.arch_extension sve-aes2
17+
.arch_extension ssve-aes
18+
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
19+
// CHECK: aesdimc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]

‎llvm/test/MC/AArch64/SVE2p1/aesd-diagnostics.s‎

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid vector list
5+
6+
aesd {z0.b-z2.b}, {z0.b-z2.b}, z0.q[0]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: aesd {z0.b-z2.b}, {z0.b-z2.b}, z0.q[0]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
aesd {z0.d-z1.d}, {z0.d-z1.d}, z0.q[0]
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13+
// CHECK-NEXT: aesd {z0.d-z1.d}, {z0.d-z1.d}, z0.q[0]
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
aesd {z0.s-z3.s}, {z0.s-z3.s}, z0.q[0]
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
18+
// CHECK-NEXT: aesd {z0.s-z3.s}, {z0.s-z3.s}, z0.q[0]
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
aesd {z0.b-z0.b}, {z0.b-z0.b}, z0.q[0]
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
23+
// CHECK-NEXT: aesd {z0.b-z0.b}, {z0.b-z0.b}, z0.q[0]
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
aesd {z3.b-z7.b}, {z3.b-z7.b}, z0.q[0]
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
28+
// CHECK-NEXT: aesd {z3.b-z7.b}, {z3.b-z7.b}, z0.q[0]
29+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
aesd {z3.b-z4.b}, {z3.b-z4.b}, z0.q[0]
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
33+
// CHECK-NEXT: aesd {z3.b-z4.b}, {z3.b-z4.b}, z0.q[0]
34+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35+
36+
aesd {z5.b-z8.b}, {z5.b-z8.b}, z0.q[0]
37+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
38+
// CHECK-NEXT: aesd {z5.b-z8.b}, {z5.b-z8.b}, z0.q[0]
39+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40+
41+
// --------------------------------------------------------------------------//
42+
// Invalid second source vector width
43+
44+
aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.d[0]
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
46+
// CHECK-NEXT: aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.d[0]
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48+
49+
aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.s[0]
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
51+
// CHECK-NEXT: aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.s[0]
52+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53+
54+
// --------------------------------------------------------------------------//
55+
// Invalid immediate index
56+
57+
aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
58+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
59+
// CHECK-NEXT: aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
60+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
61+
62+
aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[-1]
63+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
64+
// CHECK-NEXT: aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[-1]
65+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
66+
67+
// --------------------------------------------------------------------------//
68+
// Source and Destination Registers must match
69+
70+
aesd {z0.b-z1.b}, {z2.b-z3.b}, z0.q[0]
71+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
72+
// CHECK-NEXT: aesd {z0.b-z1.b}, {z2.b-z3.b}, z0.q[0]
73+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
74+
75+
aesd {z0.b-z3.b}, {z4.b-z7.b}, z0.q[0]
76+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
77+
// CHECK-NEXT: aesd {z0.b-z3.b}, {z4.b-z7.b}, z0.q[0]
78+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
79+
80+
aesd {z0.b-z3.b}, {z0.h-z3.h}, z0.q[0]
81+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
82+
// CHECK-NEXT: aesd {z0.b-z3.b}, {z0.h-z3.h}, z0.q[0]
83+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p1/aesd.s‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+ssve-aes < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve-aes2,+sve2p1 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve-aes2,+sve2p1 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve-aes2,+sve2p1 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
17+
// x2
18+
aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0] // 01000101-00100010-11101100-00000000
19+
// CHECK-INST: aesd { z0.b, z1.b }, { z0.b, z1.b }, z0.q[0]
20+
// CHECK-ENCODING: [0x00,0xec,0x22,0x45]
21+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
22+
// CHECK-UNKNOWN: 4522ec00 <unknown>
23+
24+
aesd {z20.b-z21.b}, {z20.b-z21.b}, z10.q[2] // 01000101-00110010-11101101-01010100
25+
// CHECK-INST: aesd { z20.b, z21.b }, { z20.b, z21.b }, z10.q[2]
26+
// CHECK-ENCODING: [0x54,0xed,0x32,0x45]
27+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
28+
// CHECK-UNKNOWN: 4532ed54 <unknown>
29+
30+
aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3] // 01000101-00111010-11101111-11111110
31+
// CHECK-INST: aesd { z30.b, z31.b }, { z30.b, z31.b }, z31.q[3]
32+
// CHECK-ENCODING: [0xfe,0xef,0x3a,0x45]
33+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
34+
// CHECK-UNKNOWN: 453aeffe <unknown>
35+
36+
// x4
37+
aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0] // 01000101-00100110-11101100-00000000
38+
// CHECK-INST: aesd { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
39+
// CHECK-ENCODING: [0x00,0xec,0x26,0x45]
40+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
41+
// CHECK-UNKNOWN: 4526ec00 <unknown>
42+
43+
aesd {z20.b-z23.b}, {z20.b-z23.b}, z13.q[1] // 01000101-00101110-11101101-10110100
44+
// CHECK-INST: aesd { z20.b - z23.b }, { z20.b - z23.b }, z13.q[1]
45+
// CHECK-ENCODING: [0xb4,0xed,0x2e,0x45]
46+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
47+
// CHECK-UNKNOWN: 452eedb4 <unknown>
48+
49+
aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3] // 01000101-00111110-11101111-11111100
50+
// CHECK-INST: aesd { z28.b - z31.b }, { z28.b - z31.b }, z31.q[3]
51+
// CHECK-ENCODING: [0xfc,0xef,0x3e,0x45]
52+
// CHECK-ERROR: instruction requires: sve2p1 or ssve-aes sve-aes2
53+
// CHECK-UNKNOWN: 453eeffc <unknown>

‎llvm/test/MC/AArch64/SVE2p1/aesdimc-diagnostics.s‎

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve-aes2,+sve2p1 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid vector list
5+
6+
aesdimc {z0.b-z2.b}, {z0.b-z2.b}, z0.q[0]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: aesdimc {z0.b-z2.b}, {z0.b-z2.b}, z0.q[0]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
aesdimc {z0.d-z1.d}, {z0.d-z1.d}, z0.q[0]
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13+
// CHECK-NEXT: aesdimc {z0.d-z1.d}, {z0.d-z1.d}, z0.q[0]
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
aesdimc {z0.s-z3.s}, {z0.s-z3.s}, z0.q[0]
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
18+
// CHECK-NEXT: aesdimc {z0.s-z3.s}, {z0.s-z3.s}, z0.q[0]
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
aesdimc {z0.b-z0.b}, {z0.b-z0.b}, z0.q[0]
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
23+
// CHECK-NEXT: aesdimc {z0.b-z0.b}, {z0.b-z0.b}, z0.q[0]
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
aesdimc {z3.b-z7.b}, {z3.b-z7.b}, z0.q[0]
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
28+
// CHECK-NEXT: aesdimc {z3.b-z7.b}, {z3.b-z7.b}, z0.q[0]
29+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
aesdimc {z3.b-z4.b}, {z3.b-z4.b}, z0.q[0]
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
33+
// CHECK-NEXT: aesdimc {z3.b-z4.b}, {z3.b-z4.b}, z0.q[0]
34+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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aesdimc {z5.b-z8.b}, {z5.b-z8.b}, z0.q[0]
37+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
38+
// CHECK-NEXT: aesdimc {z5.b-z8.b}, {z5.b-z8.b}, z0.q[0]
39+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid second source vector width
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aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.d[0]
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
46+
// CHECK-NEXT: aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.d[0]
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.s[0]
50+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
51+
// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.s[0]
52+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate index
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aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
58+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
59+
// CHECK-NEXT: aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
60+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
64+
// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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aesdimc {z0.b-z1.b}, {z2.b-z3.b}, z0.q[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
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// CHECK-NEXT: aesdimc {z0.b-z1.b}, {z2.b-z3.b}, z0.q[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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aesdimc {z0.b-z3.b}, {z4.b-z7.b}, z0.q[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
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// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z4.b-z7.b}, z0.q[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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aesdimc {z0.b-z3.b}, {z0.h-z3.h}, z0.q[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.h-z3.h}, z0.q[0]
83+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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