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[RISCV] Support XSfmm C intrinsics
In this version of intrinsics, users need to manage the life time of tiles on their own, compiler doesn't have tile type for variables not only for design simplicity but also preventing users to write bad performance code that could potentially having tile spills which are quite expensive in terms of cycles.
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‎clang/include/clang/Basic/riscv_sifive_vector.td‎

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,10 @@
1414

1515
include "riscv_vector_common.td"
1616

17+
class IsFloat<string type> {
18+
bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"), !eq(type, "y"));
19+
}
20+
1721
//===----------------------------------------------------------------------===//
1822
// Instruction definitions
1923
//===----------------------------------------------------------------------===//
@@ -198,3 +202,169 @@ let ManualCodegen = [{
198202
defm sf_vfnrclip_xu_f_qf : RVVVFNRCLIPBuiltinSet<"Uv", "UvFqf", "c">;
199203
}
200204
}
205+
206+
multiclass RVVSFTileLoadStoreBuiltinSet<list<string> types,
207+
list<string> RequiredFeatures = []> {
208+
let OverloadedName = NAME,
209+
Name = NAME,
210+
IRName = NAME,
211+
Log2LMUL = [0],
212+
HasMasked = false,
213+
ManualCodegen = [{IntrinsicTypes = {Ops.back()->getType()};}] in
214+
foreach type = types in {
215+
let RequiredFeatures = !listconcat(RequiredFeatures,
216+
!cond(!eq(type, "x"): ["Zvfhmin"],
217+
!eq(type, "y"): ["Zvfbfmin"],
218+
true: []<string>)) in {
219+
def : RVVBuiltin<"e", "0zPCe", type>;
220+
if !not(IsFloat<type>.val) then
221+
def : RVVBuiltin<"Ue", "0zPCUe", type>;
222+
}
223+
}
224+
}
225+
226+
multiclass RVVSFTileMoveBuiltinSet<list<list<string>> suffixes_prototypes,
227+
list<int> intrinsic_types,
228+
string type,
229+
list<string> RequiredFeatures = []> {
230+
foreach sp = suffixes_prototypes in
231+
let RequiredFeatures = !listconcat(RequiredFeatures,
232+
!cond(!eq(type, "x"): ["Zvfhmin"],
233+
!eq(type, "y"): ["Zvfbfmin"],
234+
true: []<string>)),
235+
SupportOverloading = false,
236+
HasMasked = false,
237+
Name = NAME,
238+
IRName = NAME,
239+
HasVL = true,
240+
Log2LMUL = [3],
241+
IntrinsicTypes = intrinsic_types in
242+
def : RVVBuiltin<sp[0], sp[1], type>;
243+
}
244+
245+
multiclass RVVSFTileMoveVTBuiltinSet<list<string> RequiredFeatures = []> {
246+
foreach type = ["c", "s", "i", "l"] in
247+
defm NAME :
248+
RVVSFTileMoveBuiltinSet<[["v", "vz"], ["Uv", "Uvz"]], [-1], type,
249+
RequiredFeatures>;
250+
foreach type = ["x", "y", "f", "d"] in
251+
defm NAME :
252+
RVVSFTileMoveBuiltinSet<[["v", "vz"]], [-1], type, RequiredFeatures>;
253+
}
254+
255+
multiclass RVVSFTileMoveTVBuiltinSet<list<string> RequiredFeatures = []> {
256+
let SupportOverloading = true, OverloadedName = NAME in {
257+
foreach type = ["c", "s", "i", "l"] in
258+
defm NAME :
259+
RVVSFTileMoveBuiltinSet<[["v", "0zv"], ["Uv", "0zUv"]], [1], type,
260+
RequiredFeatures>;
261+
foreach type = ["x", "y", "f", "d"] in
262+
defm NAME :
263+
RVVSFTileMoveBuiltinSet<[["v", "0zv"]], [1], type, RequiredFeatures>;
264+
}
265+
}
266+
267+
multiclass RVVOp0Op1Op2BuiltinSet<string intrinsic_name, string type_range,
268+
list<list<string>> suffixes_prototypes>
269+
: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1, 2]>;
270+
271+
multiclass RVVSFMatMulBuiltinSet<string prototype, string suffix,
272+
string type_range, list<int> widens> {
273+
foreach widen = widens in
274+
let OverloadedName = NAME,
275+
TWiden = widen,
276+
HasVL = false,
277+
Log2LMUL = [3],
278+
HasMasked = false in
279+
defm NAME : RVVOp0Op1Op2BuiltinSet<NAME, type_range,
280+
[[!strconcat("w", !cast<string>(widen)), suffix, prototype]]>;
281+
}
282+
283+
multiclass RVVSFMatMulFloatBuiltinSet<string name, string prototype, string suffix,
284+
list<string> type_range, int widen> {
285+
// Currently the XSfmm spec doesn't support w8.
286+
foreach type = type_range in
287+
let OverloadedName = name # !strconcat("_w", !cast<string>(widen)),
288+
TWiden = widen,
289+
HasVL = false,
290+
Log2LMUL = [3],
291+
Name = name # "_" # !strconcat("w", !cast<string>(widen)),
292+
HasMasked = false in
293+
defm : RVVOp0Op1BuiltinSet<name, type, [["", suffix, prototype]]>;
294+
}
295+
296+
multiclass RVVSFVTZeroBuiltinSet {
297+
let SupportOverloading = false,
298+
HasVL = false,
299+
HasMasked = false,
300+
Name = NAME,
301+
IRName = NAME,
302+
Log2LMUL = [0] in
303+
defm : RVVOp0BuiltinSet<NAME, "i", [["", "", "0Kzzzzz"]]>;
304+
}
305+
306+
multiclass RVVSFVTDiscardBuiltinSet {
307+
let SupportOverloading = false,
308+
HasVL = false,
309+
HasMasked = false,
310+
Name = NAME,
311+
IRName = NAME,
312+
Log2LMUL = [0] in
313+
defm : RVVBuiltinSet<NAME, "i", [["", "", "0"]], []>;
314+
}
315+
316+
let RequiredFeatures = ["Xsfmmbase"] in {
317+
let SupportOverloading = false,
318+
HasVL = false,
319+
HasMasked = false,
320+
Log2LMUL = [0],
321+
ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
322+
{
323+
// let HasBuiltinAlias = false in
324+
def sf_vsettnt : RVVBuiltin<"", "zzKzKz", "i">;
325+
def sf_vsettm : RVVBuiltin<"", "zzKzKz", "i">;
326+
let IRName = "sf_vsettnt" in
327+
def sf_vsettn : RVVBuiltin<"", "zzKzKz", "i">;
328+
def sf_vsettk : RVVBuiltin<"", "zzKzKz", "i">;
329+
}
330+
defm sf_vtzero_t : RVVSFVTZeroBuiltinSet;
331+
defm sf_vtdiscard : RVVSFVTDiscardBuiltinSet;
332+
}
333+
334+
defm sf_vtmv_v_t : RVVSFTileMoveVTBuiltinSet<["Xsfmmbase"]>;
335+
defm sf_vtmv_t_v : RVVSFTileMoveTVBuiltinSet<["Xsfmmbase"]>;
336+
337+
defm sf_vlte8 : RVVSFTileLoadStoreBuiltinSet<["c"], ["Xsfmmbase"]>;
338+
defm sf_vlte16 : RVVSFTileLoadStoreBuiltinSet<["s", "x", "y"], ["Xsfmmbase"]>;
339+
defm sf_vlte32 : RVVSFTileLoadStoreBuiltinSet<["i", "f"], ["Xsfmmbase"]>;
340+
defm sf_vlte64 : RVVSFTileLoadStoreBuiltinSet<["l", "d"], ["Xsfmmbase"]>;
341+
342+
defm sf_vste8 : RVVSFTileLoadStoreBuiltinSet<["c"], ["Xsfmmbase"]>;
343+
defm sf_vste16 : RVVSFTileLoadStoreBuiltinSet<["s", "x", "y"], ["Xsfmmbase"]>;
344+
defm sf_vste32 : RVVSFTileLoadStoreBuiltinSet<["i", "f"], ["Xsfmmbase"]>;
345+
defm sf_vste64 : RVVSFTileLoadStoreBuiltinSet<["l", "d"], ["Xsfmmbase"]>;
346+
347+
let RequiredFeatures = ["Xsfmm32a8i"] in {
348+
defm sf_mm_u_u : RVVSFMatMulBuiltinSet<"0KzUvUvzzz", "UvUv", "c", [4]>;
349+
defm sf_mm_s_u : RVVSFMatMulBuiltinSet<"0KzvUvzzz", "vUv", "c", [4]>;
350+
defm sf_mm_u_s : RVVSFMatMulBuiltinSet<"0KzUvvzzz", "Uvv", "c", [4]>;
351+
defm sf_mm_s_s : RVVSFMatMulBuiltinSet<"0Kzvvzzz", "vv", "c", [4]>;
352+
353+
}
354+
355+
let RequiredFeatures = ["Xsfmm32a16f"] in
356+
defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["x", "y"], 2>;
357+
358+
let RequiredFeatures = ["Xsfmm32a32f"] in
359+
defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["f"], 1>;
360+
361+
let RequiredFeatures = ["Xsfmm32a8f"] in
362+
foreach e1 = [5, 4] in
363+
foreach e2 = [5, 4] in
364+
let OverloadedName = "sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2) in
365+
defm : RVVSFMatMulFloatBuiltinSet<
366+
"sf_mm_e" # e1 # "m" # !sub(7, e1) # "_e" # e2 # "m" # !sub(7, e2),
367+
"0KzUvUvzzz", "UvUv", ["c"], 4>;
368+
369+
let RequiredFeatures = ["Xsfmm64a64f"] in
370+
defm : RVVSFMatMulFloatBuiltinSet<"sf_mm_f_f", "0Kzvvzzz", "v", ["d"], 1>;

‎clang/include/clang/Basic/riscv_vector_common.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -245,6 +245,9 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
245245
// Set to true if the builtin has a parameter that models floating-point
246246
// rounding mode control
247247
bit HasFRMRoundModeOp = false;
248+
249+
// TWiden for XSfmm.
250+
int TWiden = 0;
248251
}
249252

250253
// This is the code emitted in the header.

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -403,6 +403,7 @@ class RVVIntrinsic {
403403
std::vector<int64_t> IntrinsicTypes;
404404
unsigned NF = 1;
405405
Policy PolicyAttrs;
406+
unsigned TWiden = 0;
406407

407408
public:
408409
RVVIntrinsic(llvm::StringRef Name, llvm::StringRef Suffix,
@@ -411,8 +412,8 @@ class RVVIntrinsic {
411412
bool HasVL, PolicyScheme Scheme, bool SupportOverloading,
412413
bool HasBuiltinAlias, llvm::StringRef ManualCodegen,
413414
const RVVTypes &Types,
414-
const std::vector<int64_t> &IntrinsicTypes,
415-
unsigned NF, Policy PolicyAttrs, bool HasFRMRoundModeOp);
415+
const std::vector<int64_t> &IntrinsicTypes, unsigned NF,
416+
Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden);
416417
~RVVIntrinsic() = default;
417418

418419
RVVTypePtr getOutputType() const { return OutputType; }
@@ -436,6 +437,7 @@ class RVVIntrinsic {
436437
llvm::StringRef getManualCodegen() const { return ManualCodegen; }
437438
PolicyScheme getPolicyScheme() const { return Scheme; }
438439
unsigned getNF() const { return NF; }
440+
unsigned getTWiden() const { return TWiden; }
439441
const std::vector<int64_t> &getIntrinsicTypes() const {
440442
return IntrinsicTypes;
441443
}
@@ -508,6 +510,12 @@ enum RVVRequire {
508510
RVV_REQ_Zvfbfwma,
509511
RVV_REQ_Zvfbfmin,
510512
RVV_REQ_Zvfh,
513+
RVV_REQ_Xsfmmbase,
514+
RVV_REQ_Xsfmm32a8f,
515+
RVV_REQ_Xsfmm32a16f,
516+
RVV_REQ_Xsfmm32a32f,
517+
RVV_REQ_Xsfmm64a64f,
518+
RVV_REQ_Xsfmm32a8i,
511519
RVV_REQ_Experimental,
512520
RVV_REQ_NUM,
513521
};

‎clang/lib/CodeGen/TargetBuiltins/RISCV.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,8 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
188188
bool IsMasked = false;
189189
// This is used by segment load/store to determine it's llvm type.
190190
unsigned SegInstSEW = 8;
191+
// This is used by XSfmm.
192+
unsigned TWiden = 0;
191193

192194
// Required for overloaded intrinsics.
193195
llvm::SmallVector<llvm::Type *, 2> IntrinsicTypes;

‎clang/lib/Headers/sifive_vector.h‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,4 +115,60 @@
115115
#endif
116116
#endif
117117

118+
#define __riscv_sf_vsettnt_e8w1(atn) __riscv_sf_vsettnt(atn, 0, 1);
119+
#define __riscv_sf_vsettnt_e8w2(atn) __riscv_sf_vsettnt(atn, 0, 2);
120+
#define __riscv_sf_vsettnt_e8w4(atn) __riscv_sf_vsettnt(atn, 0, 3);
121+
#define __riscv_sf_vsettnt_e16w1(atn) __riscv_sf_vsettnt(atn, 1, 1);
122+
#define __riscv_sf_vsettnt_e16w2(atn) __riscv_sf_vsettnt(atn, 1, 2);
123+
#define __riscv_sf_vsettnt_e16w4(atn) __riscv_sf_vsettnt(atn, 1, 3);
124+
#define __riscv_sf_vsettnt_e32w1(atn) __riscv_sf_vsettnt(atn, 2, 1);
125+
#define __riscv_sf_vsettnt_e32w2(atn) __riscv_sf_vsettnt(atn, 2, 2);
126+
#define __riscv_sf_vsettm_e8w1(atm) __riscv_sf_vsettm(atm, 0, 1);
127+
#define __riscv_sf_vsettm_e8w2(atm) __riscv_sf_vsettm(atm, 0, 2);
128+
#define __riscv_sf_vsettm_e8w4(atm) __riscv_sf_vsettm(atm, 0, 3);
129+
#define __riscv_sf_vsettm_e16w1(atm) __riscv_sf_vsettm(atm, 1, 1);
130+
#define __riscv_sf_vsettm_e16w2(atm) __riscv_sf_vsettm(atm, 1, 2);
131+
#define __riscv_sf_vsettm_e16w4(atm) __riscv_sf_vsettm(atm, 1, 3);
132+
#define __riscv_sf_vsettm_e32w1(atm) __riscv_sf_vsettm(atm, 2, 1);
133+
#define __riscv_sf_vsettm_e32w2(atm) __riscv_sf_vsettm(atm, 2, 2);
134+
#define __riscv_sf_vsettn_e8w1(atn) __riscv_sf_vsettn(atn, 0, 1);
135+
#define __riscv_sf_vsettn_e8w2(atn) __riscv_sf_vsettn(atn, 0, 2);
136+
#define __riscv_sf_vsettn_e8w4(atn) __riscv_sf_vsettn(atn, 0, 3);
137+
#define __riscv_sf_vsettn_e16w1(atn) __riscv_sf_vsettn(atn, 1, 1);
138+
#define __riscv_sf_vsettn_e16w2(atn) __riscv_sf_vsettn(atn, 1, 2);
139+
#define __riscv_sf_vsettn_e16w4(atn) __riscv_sf_vsettn(atn, 1, 3);
140+
#define __riscv_sf_vsettn_e32w1(atn) __riscv_sf_vsettn(atn, 2, 1);
141+
#define __riscv_sf_vsettn_e32w2(atn) __riscv_sf_vsettn(atn, 2, 2);
142+
#define __riscv_sf_vsettk_e8w1(atk) __riscv_sf_vsettk(atk, 0, 1);
143+
#define __riscv_sf_vsettk_e8w2(atk) __riscv_sf_vsettk(atk, 0, 2);
144+
#define __riscv_sf_vsettk_e8w4(atk) __riscv_sf_vsettk(atk, 0, 3);
145+
#define __riscv_sf_vsettk_e16w1(atk) __riscv_sf_vsettk(atk, 1, 1);
146+
#define __riscv_sf_vsettk_e16w2(atk) __riscv_sf_vsettk(atk, 1, 2);
147+
#define __riscv_sf_vsettk_e16w4(atk) __riscv_sf_vsettk(atk, 1, 3);
148+
#define __riscv_sf_vsettk_e32w1(atk) __riscv_sf_vsettk(atk, 2, 1);
149+
#define __riscv_sf_vsettk_e32w2(atk) __riscv_sf_vsettk(atk, 2, 2);
150+
#define __riscv_sf_vtzero_t_e8w1(tile, atm, atn) \
151+
__riscv_sf_vtzero_t(tile, atm, atn, 3, 1);
152+
#define __riscv_sf_vtzero_t_e8w2(tile, atm, atn) \
153+
__riscv_sf_vtzero_t(tile, atm, atn, 3, 2);
154+
#define __riscv_sf_vtzero_t_e8w4(tile, atm, atn) \
155+
__riscv_sf_vtzero_t(tile, atm, atn, 3, 4);
156+
#define __riscv_sf_vtzero_t_e16w1(tile, atm, atn) \
157+
__riscv_sf_vtzero_t(tile, atm, atn, 4, 1);
158+
#define __riscv_sf_vtzero_t_e16w2(tile, atm, atn) \
159+
__riscv_sf_vtzero_t(tile, atm, atn, 4, 2);
160+
#define __riscv_sf_vtzero_t_e16w4(tile, atm, atn) \
161+
__riscv_sf_vtzero_t(tile, atm, atn, 4, 4);
162+
#define __riscv_sf_vtzero_t_e32w1(tile, atm, atn) \
163+
__riscv_sf_vtzero_t(tile, atm, atn, 5, 1);
164+
#define __riscv_sf_vtzero_t_e32w2(tile, atm, atn) \
165+
__riscv_sf_vtzero_t(tile, atm, atn, 5, 2);
166+
#if __riscv_v_elen >= 64
167+
#define __riscv_sf_vsettnt_e64w1(atn) __riscv_sf_vsettnt(atn, 3, 1);
168+
#define __riscv_sf_vsettm_e64w1(atm) __riscv_sf_vsettm(atm, 3, 1);
169+
#define __riscv_sf_vsettn_e64w1(atn) __riscv_sf_vsettn(atn, 3, 1);
170+
#define __riscv_sf_vsettk_e64w1(atk) __riscv_sf_vsettk(atk, 3, 1);
171+
#define __riscv_sf_vtzero_t_e64w1(tile, atm, atn) \
172+
__riscv_sf_vtzero_t(tile, atm, atn, 6, 1);
173+
#endif
118174
#endif //_SIFIVE_VECTOR_H_

‎clang/lib/Sema/SemaRISCV.cpp‎

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -244,6 +244,12 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
244244
{"zvfbfwma", RVV_REQ_Zvfbfwma},
245245
{"zvfbfmin", RVV_REQ_Zvfbfmin},
246246
{"zvfh", RVV_REQ_Zvfh},
247+
{"xsfmmbase", RVV_REQ_Xsfmmbase},
248+
{"xsfmm32a8f", RVV_REQ_Xsfmm32a8f},
249+
{"xsfmm32a16f", RVV_REQ_Xsfmm32a16f},
250+
{"xsfmm32a32f", RVV_REQ_Xsfmm32a32f},
251+
{"xsfmm64a64f", RVV_REQ_Xsfmm64a64f},
252+
{"xsfmm32a8i", RVV_REQ_Xsfmm32a8i},
247253
{"experimental", RVV_REQ_Experimental}};
248254

249255
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
@@ -679,6 +685,50 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
679685
return CheckVSetVL(1, 2);
680686
case RISCVVector::BI__builtin_rvv_vsetvlimax:
681687
return CheckVSetVL(0, 1);
688+
case RISCVVector::BI__builtin_rvv_sf_vsettnt:
689+
case RISCVVector::BI__builtin_rvv_sf_vsettm:
690+
case RISCVVector::BI__builtin_rvv_sf_vsettn:
691+
case RISCVVector::BI__builtin_rvv_sf_vsettk:
692+
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 3) ||
693+
SemaRef.BuiltinConstantArgRange(TheCall, 2, 1, 3);
694+
case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1:
695+
case RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2:
696+
case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e4m3_w4:
697+
case RISCVVector::BI__builtin_rvv_sf_mm_e5m2_e5m2_w4:
698+
case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e4m3_w4:
699+
case RISCVVector::BI__builtin_rvv_sf_mm_e4m3_e5m2_w4:
700+
case RISCVVector::BI__builtin_rvv_sf_mm_u_u_w4:
701+
case RISCVVector::BI__builtin_rvv_sf_mm_u_s_w4:
702+
case RISCVVector::BI__builtin_rvv_sf_mm_s_u_w4:
703+
case RISCVVector::BI__builtin_rvv_sf_mm_s_s_w4: {
704+
QualType Arg1Type = TheCall->getArg(1)->getType();
705+
ASTContext::BuiltinVectorTypeInfo Info =
706+
SemaRef.Context.getBuiltinVectorTypeInfo(
707+
Arg1Type->castAs<BuiltinType>());
708+
unsigned EltSize = SemaRef.Context.getTypeSize(Info.ElementType);
709+
llvm::APSInt Result;
710+
711+
// We can't check the value of a dependent argument.
712+
Expr *Arg = TheCall->getArg(0);
713+
if (Arg->isTypeDependent() || Arg->isValueDependent())
714+
return false;
715+
716+
// Check constant-ness first.
717+
if (SemaRef.BuiltinConstantArg(TheCall, 0, Result))
718+
return true;
719+
720+
// For TEW = 32, mtd can only be 0, 4, 8, 12.
721+
// For TEW = 64, mtd can only be 0, 2, 4, 6, 8, 10, 12, 14.
722+
// Only `sf_mm_f_f_w1` and `sf_mm_f_f_w2` might have TEW = 64.
723+
if ((BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w1 &&
724+
EltSize == 64) ||
725+
(BuiltinID == RISCVVector::BI__builtin_rvv_sf_mm_f_f_w2 &&
726+
EltSize == 32))
727+
return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||
728+
SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 2);
729+
return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 15) ||
730+
SemaRef.BuiltinConstantArgMultiple(TheCall, 0, 4);
731+
}
682732
case RISCVVector::BI__builtin_rvv_vget_v: {
683733
ASTContext::BuiltinVectorTypeInfo ResVecInfo =
684734
Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(

‎clang/lib/Support/RISCVVIntrinsicUtils.cpp‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -978,11 +978,12 @@ RVVIntrinsic::RVVIntrinsic(
978978
bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme,
979979
bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen,
980980
const RVVTypes &OutInTypes, const std::vector<int64_t> &NewIntrinsicTypes,
981-
unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp)
981+
unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden)
982982
: IRName(IRName), IsMasked(IsMasked),
983983
HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme),
984984
SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias),
985-
ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs) {
985+
ManualCodegen(ManualCodegen.str()), NF(NF), PolicyAttrs(NewPolicyAttrs),
986+
TWiden(TWiden) {
986987

987988
// Init BuiltinName, Name and OverloadedName
988989
BuiltinName = NewName.str();
@@ -1233,6 +1234,12 @@ llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, enum RVVRequire Require) {
12331234
STRINGIFY(RVV_REQ_Zvfbfwma)
12341235
STRINGIFY(RVV_REQ_Zvfbfmin)
12351236
STRINGIFY(RVV_REQ_Zvfh)
1237+
STRINGIFY(RVV_REQ_Xsfmmbase)
1238+
STRINGIFY(RVV_REQ_Xsfmm32a8f)
1239+
STRINGIFY(RVV_REQ_Xsfmm32a16f)
1240+
STRINGIFY(RVV_REQ_Xsfmm32a32f)
1241+
STRINGIFY(RVV_REQ_Xsfmm64a64f)
1242+
STRINGIFY(RVV_REQ_Xsfmm32a8i)
12361243
STRINGIFY(RVV_REQ_Experimental)
12371244
default:
12381245
llvm_unreachable("Unsupported RVVRequire!");

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