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[RISCV][GISel] Remove s32 input support for G_SITOFP/UITOFP on RV64. (#115236)
I plan to make i32 an illegal type for RV64 to match SelectionDAG and to remove i32 from the GPR register class. I've added a sexti32 ComplexPattern to select sext.w+fcvt.s.l as fcvt.s.w. The recently added zexti32 handles selecting and+fcvt.s.lu as fcvt.s.wu. There are still some regressions that suggest we should match g_zero_extend in zexti32.
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-383
lines changed

11 files changed

+138
-383
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,12 @@ class RISCVInstructionSelector : public InstructionSelector {
8787
ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
8888
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
8989

90+
ComplexRendererFns selectSExtBits(MachineOperand &Root, unsigned Bits) const;
91+
template <unsigned Bits>
92+
ComplexRendererFns selectSExtBits(MachineOperand &Root) const {
93+
return selectSExtBits(Root, Bits);
94+
}
95+
9096
ComplexRendererFns selectZExtBits(MachineOperand &Root, unsigned Bits) const;
9197
template <unsigned Bits>
9298
ComplexRendererFns selectZExtBits(MachineOperand &Root) const {
@@ -248,6 +254,27 @@ RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
248254
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
249255
}
250256

257+
InstructionSelector::ComplexRendererFns
258+
RISCVInstructionSelector::selectSExtBits(MachineOperand &Root,
259+
unsigned Bits) const {
260+
if (!Root.isReg())
261+
return std::nullopt;
262+
Register RootReg = Root.getReg();
263+
MachineInstr *RootDef = MRI->getVRegDef(RootReg);
264+
265+
if (RootDef->getOpcode() == TargetOpcode::G_SEXT_INREG &&
266+
RootDef->getOperand(2).getImm() == Bits) {
267+
return {
268+
{[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); }}};
269+
}
270+
271+
unsigned Size = MRI->getType(RootReg).getScalarSizeInBits();
272+
if ((Size - KB->computeNumSignBits(RootReg)) < Bits)
273+
return {{[=](MachineInstrBuilder &MIB) { MIB.add(Root); }}};
274+
275+
return std::nullopt;
276+
}
277+
251278
InstructionSelector::ComplexRendererFns
252279
RISCVInstructionSelector::selectZExtBits(MachineOperand &Root,
253280
unsigned Bits) const {

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -542,9 +542,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
542542
.libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});
543543

544544
getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
545-
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
545+
.legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {sXLen})))
546546
.widenScalarToNextPow2(1)
547-
.minScalar(1, s32)
547+
.minScalar(1, sXLen)
548548
.libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
549549
.libcallFor(ST.is64Bit(), {{s32, s128}, {s64, s128}});
550550

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,9 @@ def gi_sh2add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<2>">,
9696
def gi_sh3add_uw_op : GIComplexOperandMatcher<s32, "selectSHXADD_UWOp<3>">,
9797
GIComplexPatternEquiv<sh3add_uw_op>;
9898

99+
def gi_sexti32 : GIComplexOperandMatcher<s64, "selectSExtBits<32>">,
100+
GIComplexPatternEquiv<sexti32>;
101+
99102
def gi_zexti32 : GIComplexOperandMatcher<s64, "selectZExtBits<32>">,
100103
GIComplexPatternEquiv<zexti32>;
101104
def gi_zexti16 : GIComplexOperandMatcher<s32, "selectZExtBits<16>">,

‎llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -98,11 +98,17 @@ define double @fcvt_d_wu(i32 %a) nounwind {
9898
}
9999

100100
define double @fcvt_d_wu_load(ptr %p) nounwind {
101-
; CHECKIFD-LABEL: fcvt_d_wu_load:
102-
; CHECKIFD: # %bb.0:
103-
; CHECKIFD-NEXT: lw a0, 0(a0)
104-
; CHECKIFD-NEXT: fcvt.d.wu fa0, a0
105-
; CHECKIFD-NEXT: ret
101+
; RV32IFD-LABEL: fcvt_d_wu_load:
102+
; RV32IFD: # %bb.0:
103+
; RV32IFD-NEXT: lw a0, 0(a0)
104+
; RV32IFD-NEXT: fcvt.d.wu fa0, a0
105+
; RV32IFD-NEXT: ret
106+
;
107+
; RV64IFD-LABEL: fcvt_d_wu_load:
108+
; RV64IFD: # %bb.0:
109+
; RV64IFD-NEXT: lwu a0, 0(a0)
110+
; RV64IFD-NEXT: fcvt.d.wu fa0, a0
111+
; RV64IFD-NEXT: ret
106112
%a = load i32, ptr %p
107113
%1 = uitofp i32 %a to double
108114
ret double %1
@@ -294,7 +300,9 @@ define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
294300
; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
295301
; RV64IFD: # %bb.0:
296302
; RV64IFD-NEXT: addiw a0, a0, 1
297-
; RV64IFD-NEXT: fcvt.d.wu fa5, a0
303+
; RV64IFD-NEXT: slli a2, a0, 32
304+
; RV64IFD-NEXT: srli a2, a2, 32
305+
; RV64IFD-NEXT: fcvt.d.wu fa5, a2
298306
; RV64IFD-NEXT: fsd fa5, 0(a1)
299307
; RV64IFD-NEXT: ret
300308
%3 = add i32 %0, 1

‎llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll‎

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -101,11 +101,17 @@ define float @fcvt_s_wu(i32 %a) nounwind {
101101
}
102102

103103
define float @fcvt_s_wu_load(ptr %p) nounwind {
104-
; CHECKIF-LABEL: fcvt_s_wu_load:
105-
; CHECKIF: # %bb.0:
106-
; CHECKIF-NEXT: lw a0, 0(a0)
107-
; CHECKIF-NEXT: fcvt.s.wu fa0, a0
108-
; CHECKIF-NEXT: ret
104+
; RV32IF-LABEL: fcvt_s_wu_load:
105+
; RV32IF: # %bb.0:
106+
; RV32IF-NEXT: lw a0, 0(a0)
107+
; RV32IF-NEXT: fcvt.s.wu fa0, a0
108+
; RV32IF-NEXT: ret
109+
;
110+
; RV64IF-LABEL: fcvt_s_wu_load:
111+
; RV64IF: # %bb.0:
112+
; RV64IF-NEXT: lwu a0, 0(a0)
113+
; RV64IF-NEXT: fcvt.s.wu fa0, a0
114+
; RV64IF-NEXT: ret
109115
%a = load i32, ptr %p
110116
%1 = uitofp i32 %a to float
111117
ret float %1
@@ -266,7 +272,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
266272
; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
267273
; RV64IF: # %bb.0:
268274
; RV64IF-NEXT: addiw a0, a0, 1
269-
; RV64IF-NEXT: fcvt.s.wu fa5, a0
275+
; RV64IF-NEXT: slli a2, a0, 32
276+
; RV64IF-NEXT: srli a2, a2, 32
277+
; RV64IF-NEXT: fcvt.s.wu fa5, a2
270278
; RV64IF-NEXT: fsw fa5, 0(a1)
271279
; RV64IF-NEXT: ret
272280
%3 = add i32 %0, 1

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-f16-rv64.mir‎

Lines changed: 0 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -2,52 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
33
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
44

5-
---
6-
name: sitofp_s64_s32
7-
legalized: true
8-
regBankSelected: true
9-
tracksRegLiveness: true
10-
body: |
11-
bb.0:
12-
liveins: $x10
13-
14-
; CHECK-LABEL: name: sitofp_s64_s32
15-
; CHECK: liveins: $x10
16-
; CHECK-NEXT: {{ $}}
17-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18-
; CHECK-NEXT: [[FCVT_H_W:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_W [[COPY]], 7
19-
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_W]]
20-
; CHECK-NEXT: PseudoRET implicit $f10_h
21-
%0:gprb(s64) = COPY $x10
22-
%1:gprb(s32) = G_TRUNC %0(s64)
23-
%2:fprb(s16) = G_SITOFP %1(s32)
24-
$f10_h = COPY %2(s16)
25-
PseudoRET implicit $f10_h
26-
27-
...
28-
---
29-
name: uitofp_s64_s32
30-
legalized: true
31-
regBankSelected: true
32-
tracksRegLiveness: true
33-
body: |
34-
bb.0:
35-
liveins: $x10
36-
37-
; CHECK-LABEL: name: uitofp_s64_s32
38-
; CHECK: liveins: $x10
39-
; CHECK-NEXT: {{ $}}
40-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
41-
; CHECK-NEXT: [[FCVT_H_WU:%[0-9]+]]:fpr16 = nofpexcept FCVT_H_WU [[COPY]], 7
42-
; CHECK-NEXT: $f10_h = COPY [[FCVT_H_WU]]
43-
; CHECK-NEXT: PseudoRET implicit $f10_h
44-
%0:gprb(s64) = COPY $x10
45-
%1:gprb(s32) = G_TRUNC %0(s64)
46-
%2:fprb(s16) = G_UITOFP %1(s32)
47-
$f10_h = COPY %2(s16)
48-
PseudoRET implicit $f10_h
49-
50-
...
515
---
526
name: sitofp_s64_s64
537
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/itofp-rv64.mir‎

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -2,52 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
33
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
44

5-
---
6-
name: sitofp_s32_s32
7-
legalized: true
8-
regBankSelected: true
9-
tracksRegLiveness: true
10-
body: |
11-
bb.0:
12-
liveins: $x10
13-
14-
; CHECK-LABEL: name: sitofp_s32_s32
15-
; CHECK: liveins: $x10
16-
; CHECK-NEXT: {{ $}}
17-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18-
; CHECK-NEXT: [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[COPY]], 7
19-
; CHECK-NEXT: $f10_f = COPY [[FCVT_S_W]]
20-
; CHECK-NEXT: PseudoRET implicit $f10_f
21-
%0:gprb(s64) = COPY $x10
22-
%1:gprb(s32) = G_TRUNC %0(s64)
23-
%2:fprb(s32) = G_SITOFP %1(s32)
24-
$f10_f = COPY %2(s32)
25-
PseudoRET implicit $f10_f
26-
27-
...
28-
---
29-
name: uitofp_s32_s32
30-
legalized: true
31-
regBankSelected: true
32-
tracksRegLiveness: true
33-
body: |
34-
bb.0:
35-
liveins: $x10
36-
37-
; CHECK-LABEL: name: uitofp_s32_s32
38-
; CHECK: liveins: $x10
39-
; CHECK-NEXT: {{ $}}
40-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
41-
; CHECK-NEXT: [[FCVT_S_WU:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_WU [[COPY]], 7
42-
; CHECK-NEXT: $f10_f = COPY [[FCVT_S_WU]]
43-
; CHECK-NEXT: PseudoRET implicit $f10_f
44-
%0:gprb(s64) = COPY $x10
45-
%1:gprb(s32) = G_TRUNC %0(s64)
46-
%2:fprb(s32) = G_UITOFP %1(s32)
47-
$f10_f = COPY %2(s32)
48-
PseudoRET implicit $f10_f
49-
50-
...
515
---
526
name: sitofp_s32_s64
537
legalized: true
@@ -91,52 +45,6 @@ body: |
9145
$f10_f = COPY %1(s32)
9246
PseudoRET implicit $f10_f
9347
94-
...
95-
---
96-
name: sitofp_s64_s32
97-
legalized: true
98-
regBankSelected: true
99-
tracksRegLiveness: true
100-
body: |
101-
bb.0:
102-
liveins: $x10
103-
104-
; CHECK-LABEL: name: sitofp_s64_s32
105-
; CHECK: liveins: $x10
106-
; CHECK-NEXT: {{ $}}
107-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
108-
; CHECK-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_W [[COPY]], 0
109-
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_W]]
110-
; CHECK-NEXT: PseudoRET implicit $f10_d
111-
%0:gprb(s64) = COPY $x10
112-
%1:gprb(s32) = G_TRUNC %0(s64)
113-
%2:fprb(s64) = G_SITOFP %1(s32)
114-
$f10_d = COPY %2(s64)
115-
PseudoRET implicit $f10_d
116-
117-
...
118-
---
119-
name: uitofp_s64_s32
120-
legalized: true
121-
regBankSelected: true
122-
tracksRegLiveness: true
123-
body: |
124-
bb.0:
125-
liveins: $x10
126-
127-
; CHECK-LABEL: name: uitofp_s64_s32
128-
; CHECK: liveins: $x10
129-
; CHECK-NEXT: {{ $}}
130-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
131-
; CHECK-NEXT: [[FCVT_D_WU:%[0-9]+]]:fpr64 = nofpexcept FCVT_D_WU [[COPY]], 0
132-
; CHECK-NEXT: $f10_d = COPY [[FCVT_D_WU]]
133-
; CHECK-NEXT: PseudoRET implicit $f10_d
134-
%0:gprb(s64) = COPY $x10
135-
%1:gprb(s32) = G_TRUNC %0(s64)
136-
%2:fprb(s64) = G_UITOFP %1(s32)
137-
$f10_d = COPY %2(s64)
138-
PseudoRET implicit $f10_d
139-
14048
...
14149
---
14250
name: sitofp_s64_s64

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