[AMDGPU] Use using instead of typedef. NFC.

Author: jayfoad

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -112,7 +112,7 @@ class InstructionRule {
   virtual ~InstructionRule() = default;
 };
 
-typedef DenseMap<SUnit *, SmallVector<int, 4>> SUnitsToCandidateSGsMap;
+using SUnitsToCandidateSGsMap = DenseMap<SUnit *, SmallVector<int, 4>>;
 
 // Classify instructions into groups to enable fine tuned control over the
 // scheduler. These groups may be more specific than current SchedModel
@@ -261,8 +261,8 @@ static void resetEdges(SUnit &SU, ScheduleDAGInstrs *DAG) {
           S.getSUnit()->removePred(SP);
 }
 
-typedef std::pair<SUnit *, SmallVector<int, 4>> SUToCandSGsPair;
-typedef SmallVector<SUToCandSGsPair, 4> SUsToCandSGsVec;
+using SUToCandSGsPair = std::pair<SUnit *, SmallVector<int, 4>>;
+using SUsToCandSGsVec = SmallVector<SUToCandSGsPair, 4>;
 
 // The PipelineSolver is used to assign SUnits to SchedGroups in a pipeline
 // in non-trivial cases. For example, if the requested pipeline is

llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp

@@ -55,7 +55,7 @@ class AMDGPULibCalls {
   AssumptionCache *AC = nullptr;
   DominatorTree *DT = nullptr;
 
-  typedef llvm::AMDGPULibFunc FuncInfo;
+  using FuncInfo = llvm::AMDGPULibFunc;
 
   bool UnsafeFPMath = false;
 

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

@@ -446,10 +446,10 @@ void GCNHazardRecognizer::RecedeCycle() {
 // Helper Functions
 //===----------------------------------------------------------------------===//
 
-typedef enum { HazardFound, HazardExpired, NoHazardFound } HazardFnResult;
+using HazardFnResult = enum { HazardFound, HazardExpired, NoHazardFound };
 
-typedef function_ref<bool(const MachineInstr &, int WaitStates)> IsExpiredFn;
-typedef function_ref<unsigned int(const MachineInstr &)> GetNumWaitStatesFn;
+using IsExpiredFn = function_ref<bool(const MachineInstr &, int WaitStates)>;
+using GetNumWaitStatesFn = function_ref<unsigned int(const MachineInstr &)>;
 
 // Search for a hazard in a block and its predecessors.
 template <typename StateT>

llvm/lib/Target/AMDGPU/GCNILPSched.cpp

@@ -27,7 +27,7 @@ class GCNILPScheduler {
   };
 
   SpecificBumpPtrAllocator<Candidate> Alloc;
-  typedef simple_ilist<Candidate> Queue;
+  using Queue = simple_ilist<Candidate>;
   Queue PendingQueue;
   Queue AvailQueue;
   unsigned CurQueueId = 0;

llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp

@@ -56,13 +56,13 @@ class GCNNSAReassign : public MachineFunctionPass {
   }
 
 private:
-  typedef enum {
+  using NSA_Status = enum {
     NOT_NSA,        // Not an NSA instruction
     FIXED,          // NSA which we cannot modify
     NON_CONTIGUOUS, // NSA with non-sequential address which we can try
                     // to optimize.
     CONTIGUOUS      // NSA with all sequential address registers
-  } NSA_Status;
+  };
 
   const GCNSubtarget *ST;
 

llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp

@@ -88,7 +88,7 @@ class GCNRewritePartialRegUses : public MachineFunctionPass {
   };
 
   /// Map OldSubReg -> { RC, NewSubReg }. Used as in/out container.
-  typedef SmallDenseMap<unsigned, SubRegInfo> SubRegMap;
+  using SubRegMap = SmallDenseMap<unsigned, SubRegInfo>;
 
   /// Given register class RC and the set of used subregs as keys in the SubRegs
   /// map return new register class and indexes of right-shifted subregs as

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

@@ -32,7 +32,7 @@ MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15),
 namespace {
 
 class SIFormMemoryClauses : public MachineFunctionPass {
-  typedef DenseMap<unsigned, std::pair<unsigned, LaneBitmask>> RegUse;
+  using RegUse = DenseMap<unsigned, std::pair<unsigned, LaneBitmask>>;
 
 public:
   static char ID;