move pattern

Author: mbrkusanin

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -3548,14 +3548,7 @@ def : GCNPat <
   (vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_32:$src1))),
   (vecTy (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
 >;
-}
-
-let True16Predicate = UseRealTrue16Insts in
-def : GCNPat <
-  (vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_16:$src1))),
-  (REG_SEQUENCE VGPR_32, (Ty (IMPLICIT_DEF)), lo16, (Ty VGPR_16:$src1), hi16)
->;
-
+} // End True16Predicate = ...
 } // End foreach Ty = ...
 } // End AddedComplexity = 1
 
@@ -3615,6 +3608,10 @@ def : GCNPat <
   (vecTy (DivergentBinFrag<build_vector> (Ty VGPR_16:$src0), (Ty undef))),
   (REG_SEQUENCE VGPR_32, $src0, lo16, (Ty (IMPLICIT_DEF)), hi16)
 >;
+def : GCNPat <
+  (vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_16:$src1))),
+  (REG_SEQUENCE VGPR_32, (Ty (IMPLICIT_DEF)), lo16, (Ty VGPR_16:$src1), hi16)
+>;
 }
 
 // Take the lower 16 bits from V[0] and the upper 16 bits from V[1]