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llvm/lib/CodeGen/RegisterCoalescer.cpp

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1474,29 +1474,22 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
14741474
//
14751475
// The implicit-def of the super register may have been reduced to
14761476
// subregisters depending on the uses.
1477-
1478-
TinyPtrVector<MachineOperand *> NewMIImpDefDestReg;
1479-
[[maybe_unused]] unsigned NewMIOpCount = NewMI.getNumOperands();
1480-
1481-
SmallVector<MCRegister, 4> NewMIImplDefs;
1477+
SmallVector<std::pair<unsigned, MCRegister>, 4> NewMIImplDefs;
14821478
for (unsigned i = NewMI.getDesc().getNumOperands(),
14831479
e = NewMI.getNumOperands();
14841480
i != e; ++i) {
14851481
MachineOperand &MO = NewMI.getOperand(i);
14861482
if (MO.isReg() && MO.isDef()) {
14871483
assert(MO.isImplicit());
14881484
if (MO.getReg().isPhysical()) {
1489-
if (MO.getReg() == DstReg)
1490-
NewMIImpDefDestReg.push_back(&MO);
1491-
14921485
assert(MO.isImplicit() && MO.getReg().isPhysical() &&
14931486
(MO.isDead() ||
14941487
(DefSubIdx &&
14951488
((TRI->getSubReg(MO.getReg(), DefSubIdx) ==
14961489
MCRegister((unsigned)NewMI.getOperand(0).getReg())) ||
14971490
TRI->isSubRegisterEq(NewMI.getOperand(0).getReg(),
14981491
MO.getReg())))));
1499-
NewMIImplDefs.push_back(MO.getReg().asMCReg());
1492+
NewMIImplDefs.push_back({i, MO.getReg().asMCReg()});
15001493
} else {
15011494
assert(MO.getReg() == NewMI.getOperand(0).getReg());
15021495

@@ -1649,27 +1642,22 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
16491642
NewMI.getOperand(0).setIsDead(true);
16501643

16511644
bool HasDefMatchingCopy = false;
1652-
if (!NewMIImpDefDestReg.empty()) {
1653-
// Assert to check MachineOperand*s have not been invalidated.
1654-
assert(
1655-
NewMIOpCount == NewMI.getNumOperands() &&
1656-
"Expected NewMI operands not to be appended/removed at this point");
1657-
// If NewMI has an implicit-def of a super-register of the CopyDstReg,
1658-
// we must also mark that as dead since it is not going to used as a
1659-
// result of this remat.
1660-
for (MachineOperand *MO : NewMIImpDefDestReg) {
1661-
if (MO->getReg() != CopyDstReg)
1662-
MO->setIsDead(true);
1663-
else
1664-
HasDefMatchingCopy = true;
1665-
}
1645+
for (auto [OpIndex, Reg] : NewMIImplDefs) {
1646+
if (Reg != DstReg.asMCReg())
1647+
continue;
1648+
// Also, if CopyDstReg is a sub-register of DstReg (and it is defined), we
1649+
// must mark DstReg as dead since it is not going to used as a result of
1650+
// this remat.
1651+
if (DstReg != CopyDstReg)
1652+
NewMI.getOperand(OpIndex).setIsDead(true);
1653+
else
1654+
HasDefMatchingCopy = true;
16661655
}
16671656

16681657
// If NewMI does not already have an implicit-def CopyDstReg add one now.
1669-
if (!HasDefMatchingCopy) {
1658+
if (!HasDefMatchingCopy)
16701659
NewMI.addOperand(MachineOperand::CreateReg(
16711660
CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
1672-
}
16731661

16741662
// Record small dead def live-ranges for all the subregisters
16751663
// of the destination register.
@@ -1700,7 +1688,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
17001688
NewMI.addOperand(MO);
17011689

17021690
SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
1703-
for (MCRegister Reg : NewMIImplDefs) {
1691+
for (MCRegister Reg : make_second_range(NewMIImplDefs)) {
17041692
for (MCRegUnit Unit : TRI->regunits(Reg))
17051693
if (LiveRange *LR = LIS->getCachedRegUnit(Unit))
17061694
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());

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