@@ -1894,6 +1894,21 @@ def btihint_op : Operand<i32> {
18941894 }];
18951895}
18961896
1897+ def CMHPriorityHintOperand : AsmOperandClass {
1898+ let Name = "CMHPriorityHint";
1899+ let ParserMethod = "tryParseCMHPriorityHint";
1900+ }
1901+
1902+ def CMHPriorityHint_op : Operand<i32> {
1903+ let ParserMatchClass = CMHPriorityHintOperand;
1904+ let PrintMethod = "printCMHPriorityHintOp";
1905+ let MCOperandPredicate = [{
1906+ if (!MCOp.isImm())
1907+ return false;
1908+ return AArch64CMHPriorityHint::lookupCMHPriorityHintByEncoding(MCOp.getImm()) != nullptr;
1909+ }];
1910+ }
1911+
18971912class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
18981913 "mrs", "\t$Rt, $systemreg"> {
18991914 bits<16> systemreg;
@@ -4636,6 +4651,48 @@ multiclass StorePairOffset<bits<2> opc, bit V, RegisterOperand regtype,
46364651 GPR64sp:$Rn, 0)>;
46374652}
46384653
4654+ class BaseLoadStoreAcquirePairOffset<bits<4> opc, bit L, dag oops, dag iops,
4655+ string asm>
4656+ : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, #0]", "", []> {
4657+ bits<5> Rt;
4658+ bits<5> Rt2;
4659+ bits<5> Rn;
4660+ let Inst{31-23} = 0b110110010;
4661+ let Inst{22} = L;
4662+ let Inst{21} = 0b0;
4663+ let Inst{20-16} = Rt2;
4664+ let Inst{15-12} = opc;
4665+ let Inst{11-10} = 0b10;
4666+ let Inst{9-5} = Rn;
4667+ let Inst{4-0} = Rt;
4668+ }
4669+
4670+ multiclass LoadAcquirePairOffset<bits<4> opc, string asm> {
4671+ let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
4672+ def i : BaseLoadStoreAcquirePairOffset<opc, 0b1,
4673+ (outs GPR64:$Rt, GPR64:$Rt2),
4674+ (ins GPR64sp:$Rn), asm>,
4675+ Sched<[WriteAtomic, WriteLDHi]>;
4676+
4677+ def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4678+ (!cast<Instruction>(NAME # "i") GPR64:$Rt, GPR64:$Rt2,
4679+ GPR64sp:$Rn)>;
4680+ }
4681+
4682+
4683+ multiclass StoreAcquirePairOffset<bits<4> opc, string asm> {
4684+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
4685+ def i : BaseLoadStoreAcquirePairOffset<opc, 0b0, (outs),
4686+ (ins GPR64:$Rt, GPR64:$Rt2,
4687+ GPR64sp:$Rn),
4688+ asm>,
4689+ Sched<[WriteSTP]>;
4690+
4691+ def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4692+ (!cast<Instruction>(NAME # "i") GPR64:$Rt, GPR64:$Rt2,
4693+ GPR64sp:$Rn)>;
4694+ }
4695+
46394696// (pre-indexed)
46404697class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
46414698 string asm>
@@ -13227,3 +13284,34 @@ multiclass SIMDThreeSameVectorFP8MatrixMul<string asm>{
1322713284 let Predicates = [HasNEON, HasF8F32MM];
1322813285 }
1322913286}
13287+
13288+ //----------------------------------------------------------------------------
13289+ // Contention Management Hints - FEAT_CMH
13290+ //----------------------------------------------------------------------------
13291+
13292+ class SHUHInst<string asm> : I<
13293+ (outs),
13294+ (ins CMHPriorityHint_op:$priority),
13295+ asm, "\t$priority", "", []>, Sched<[]> {
13296+ bits<1> priority;
13297+ let Inst{31-12} = 0b11010101000000110010;
13298+ let Inst{11-8} = 0b0110;
13299+ let Inst{7-6} = 0b01;
13300+ let Inst{5} = priority;
13301+ let Inst{4-0} = 0b11111;
13302+ }
13303+
13304+ multiclass SHUH<string asm> {
13305+ def NAME : SHUHInst<asm>;
13306+ def : InstAlias<asm, (!cast<Instruction>(NAME) 0), 1>;
13307+ }
13308+
13309+ class STCPHInst<string asm> : I<
13310+ (outs),
13311+ (ins),
13312+ asm, "", "", []>, Sched<[]> {
13313+ let Inst{31-12} = 0b11010101000000110010;
13314+ let Inst{11-8} = 0b0110;
13315+ let Inst{7-5} = 0b100;
13316+ let Inst{4-0} = 0b11111;
13317+ }
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